Patents by Inventor Yin Liu

Yin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer bonding process and structure
    Patent number: 10128209
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang
  • Registration for System Level Search User Interface
    Publication number: 20180322220
    Abstract: A system level search module receives system level search user interface registration information for an application of the computing device. The registration information includes an indication of how the system level search module can launch the application. The registration information is added to a registration store, and the application is included as one of one or more applications that can be searched using the system level search user interface.
    Type: Application
    Filed: July 16, 2018
    Publication date: November 8, 2018
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Priya Vaidyanathan, Brian E. Uphoff, Brandon H. Paddock, Stephanie M. Monk, Dona Sarkar, Wentao Chen, Edward Boyle Averett, Manav Mishra, Derek S. Gebhard, Richard Jacob White, Yin Liu
  • Successive approximation register analog-to-digital converter capable of accelerating reset
    Patent number: 10110243
    Abstract: A successive approximation register analog-to-digital converter capable of accelerating reset comprises: a sampling circuit generating at least one output signal(s) according to at least one input signal(s); a comparator generating at least one comparator output signal(s) according to the at least one output signal(s) and a reset signal; a control circuit controlling the operation of the sampling circuit according to the at least one comparator output signal(s) or the equivalent thereof, and generating the reset signal; a first reset wire circuit outputting the reset signal to the comparator so that a first circuit of the comparator is reset when the value of the reset signal is a first value; and a second reset wire circuit outputting the reset signal to the comparator so that a second circuit of the comparator is synchronously reset when the value of the reset signal is the first value.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 23, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yun-Tse Chen, Kai-Yin Liu
  • Hybrid bonding systems and methods for semiconductor wafers
    Patent number: 10103122
    Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Method and apparatus for image sensor packaging
    Patent number: 10096645
    Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond pad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding strength between the sensor and the ASIC.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Ping-Yin Liu, Calvin Yi-Ping Chao, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Lan-Lin Chao
  • 3D integrated circuit and methods of forming the same
    Patent number: 10090196
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Resistance calibration circuit and device
    Patent number: 10079591
    Abstract: The present invention discloses a resistance calibration circuit.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 18, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Kai-Yin Liu, Hui-Min Huang
  • Registration for system level search user interface
    Patent number: 10073927
    Abstract: A system level search module receives system level search user interface registration information for an application of the computing device. The registration information includes an indication of how the system level search module can launch the application. The registration information is added to a registration store, and the application is included as one of one or more applications that can be searched using the system level search user interface.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: September 11, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Priya Vaidyanathan, Brian E. Uphoff, Brandon H. Paddock, Stephanie M. Monk, Dona Sarkar, Wentao Chen, Edward Boyle Averett, Manav Mishra, Derek S. Gebhard, Richard Jacob White, Yin Liu
  • Systems and methods for determining the trustworthiness of files within organizations
    Patent number: 10055586
    Abstract: The disclosed computer-implemented method for determining the trustworthiness of files within organizations may include (1) identifying a file on a computing device within multiple computing devices managed by an organization, (2) in response to identifying the file, identifying at least one additional computing device within the multiple computing devices that is potentially associated with the file, (3) distributing at least a portion of the file to a user of the additional computing device with a request to receive an indication of the trustworthiness of the file, and then (4) receiving, from the additional computing device, a response that indicates the trustworthiness of the file. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 21, 2018
    Assignee: Symantec Corporation
    Inventors: Kevin Roundy, Sandeep Bhatkar, Christopher Gates, Anand Kashyap, Yin Liu, Aleatha Parker-Wood, Leylya Yumer
  • Bond Rings in Semiconductor Devices and Methods of Forming Same
    Publication number: 20180230003
    Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.
    Type: Application
    Filed: April 13, 2018
    Publication date: August 16, 2018
    Inventors: Chih-Ming Chen, Ping-Yin Liu, Chung-Yi Yu, Yeur-Luen Tu
  • Apparatus and method for wafer level bonding
    Patent number: 10049901
    Abstract: A method includes placing a first wafer onto a surface of a first wafer chuck, the first wafer chuck including multiple first profile control zones separated by one or more shared flexible membranes. The method also includes setting a first profile of the surface of the first wafer chuck. Setting a first profile of the surface of the first wafer chuck includes adjusting a first volume of a first profile control zone of the multiple first profile control zones. Setting a first profile of the surface of the first wafer chuck also includes adjusting a second volume of a second profile control zone of the multiple first profile control zones, the first volume of the first profile control zone being adjusted independently from the second volume of the second profile control zone, and the second adjustable volume encircling the first adjustable volume.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Yen-Chang Chu, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Ru-Liang Lee
  • Multiple Metal Layer Semiconductor Device and Low Temperature Stacking Method of Fabricating the Same
    Publication number: 20180226337
    Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.
    Type: Application
    Filed: February 2, 2018
    Publication date: August 9, 2018
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Alignment systems and wafer bonding systems and methods
    Patent number: 10037968
    Abstract: Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Xin-Hua Huang, Xiaomeng Chen, Ping-Yin Liu, Lan-Lin Chao
  • Practical and dynamic approach to enterprise hardening
    Patent number: 10025937
    Abstract: Techniques are disclosed for dynamically managing hardening policies in a client computer (e.g., of an enterprise network). A hardening management application monitors activity on the client computer that is associated with a first hardening policy. The monitored activity is evaluated based on one or more metrics. Upon determining that at least one of the metrics is outside of a tolerance specified in the first hardening policy, the client computer is associated with a second hardening policy. The client computer is reconfigured based on the second hardening policy.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 17, 2018
    Assignee: Symantec Corporation
    Inventors: Anand Kashyap, Kevin A. Roundy, Sandeep Bhatkar, Aleatha Parker-Wood, Christopher Gates, Yin Liu, Leylya Yumer
  • OPERATING VOLTAGE SWITCHING DEVICE
    Publication number: 20180196458
    Abstract: An operating voltage switching device includes a first current mirror circuit generating a corresponding sensing current according to an input current; a comparator comparing a reference voltage with a voltage at a node of the first current mirror circuit to generate a comparison signal; a first power domain providing a first output current to an internal circuit according to the sensing current; a second power domain providing a second output current to the internal circuit according to the sensing current; and a power domain selecting circuit, which is coupled to the comparator, the first power domain and the second power domain, and selects to enable the first power domain or the second power domain according to the comparison signal; wherein the sensing current is not greater than the input current.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 12, 2018
    Inventors: Chih-Cheng LIN, KAI-YIN LIU, Hui-Min HUANG
  • Graphene pellicle for extreme ultraviolet lithography
    Patent number: 10012899
    Abstract: A method includes depositing a first material layer over a first substrate; and depositing a graphene layer over the first material layer. The method further includes depositing an amorphous silicon layer over the graphene layer and bonding the amorphous silicon layer to a second substrate, thereby forming an assembly. The method further includes annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer. The method further includes removing the first substrate from the assembly and removing the first material layer from the assembly, thereby exposing the graphene layer.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen, Chue San Yoo, Jong-Yuh Chang, Chia-Shiung Tsai, Ping-Yin Liu, Hsin-Chang Lee, Chih-Cheng Lin, Yun-Yue Lin
  • Detection Circuit for Power over Ethernet and Detection Current Generation Method Thereof
    Publication number: 20180143225
    Abstract: A detection circuit for power over Ethernet (PoE) and a detection current generation method thereof. The detection circuit for PoE is installed in power sourcing equipment (PSE), and generates a first detection current in a first detection mode to detect a power device (PD) of a first type and generates a second detection current in a second detection mode to detect a PD of a second type. The detection circuit of PoE includes a first current source group that has at least one first current source for generating part of the first detection current in the first detection mode, and a second current source group that has multiple second current sources for generating part of the first detection current in the first detection mode and generating the second detection current in the second detection mode. The first current source group does not generate current in the second detection mode.
    Type: Application
    Filed: September 25, 2017
    Publication date: May 24, 2018
    Inventors: KAI-YIN LIU, HUI-MIN HUANG
  • RESISTANCE CALIBRATION CIRCUIT AND DEVICE
    Publication number: 20180138895
    Abstract: The present invention discloses a resistance calibration circuit.
    Type: Application
    Filed: September 1, 2017
    Publication date: May 17, 2018
    Inventors: KAI-YIN LIU, HUI-MIN HUANG
  • VOLTAGE REFERENCE BUFFER CIRCUIT
    Publication number: 20180136681
    Abstract: The present invention discloses a voltage reference buffer circuit. An embodiment of the voltage reference buffer circuit includes: a first bias generator configured to generate a first bias voltage; a second bias generator configured to generate a second bias voltage different from the first bias voltage; a first driving component coupled to a high voltage terminal, the first bias generator and a reference voltage output terminal, and configured to control a reference voltage at the reference voltage output terminal according to the first bias voltage; and a second driving component coupled to the reference voltage output terminal, the second bias generator and a low voltage terminal, and configured to control a current between the reference voltage output terminal and the second driving component according to the second bias voltage.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 17, 2018
    Inventors: CHE-WEI CHANG, KAI-YIN LIU, LIANG-HUAN LEI, SHIH-HSIUNG HUANG
  • Hybrid bonding mechanisms for semiconductor wafers
    Patent number: 9960129
    Abstract: A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Szu-Ying Chen, Chen-Jong Wang, Chih-Hui Huang, Xin-Hua Huang, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen