Patents by Inventor Yin Wang

Yin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250119857
    Abstract: The present disclosure address systems and methods for improving the performance of Interest of Things (IoT) devices in receiving Beacon signals. The method includes receiving a first signal from an access point (AP) of a network environment, extracting a time synchronization value of the AP from the first signal, obtaining a local time synchronization value corresponding to the time synchronization value of the AP, and determining whether a preset condition is satisfied. The preset condition may indicate that the receiving of the first signal is to be interrupted. The method further includes in response to a determination that the preset condition is satisfied, obtaining a time synchronization offset value, adjusting the local time synchronization value based on the time synchronization offset value and the time synchronization value of the AP, and preparing to receive a second signal according to the adjusted local time synchronization value.
    Type: Application
    Filed: October 31, 2023
    Publication date: April 10, 2025
    Applicant: Beken Corporation
    Inventors: Qiang SUN, Yin WANG, Huaming JIANG, Yantao LI
  • Publication number: 20250113596
    Abstract: Embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source/drain region extending laterally from an end of the first semiconductor nanostructure, the first source/drain region having a first conductivity type; a second source/drain region extending laterally from an end of the second semiconductor nanostructure, the second source/drain region having the first conductivity type, the second source/drain region aligned vertically with the first source/drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Inventors: Jui-Chien Huang, Cheng-Yin Wang, Wei-Cheng Lin, Kao-Cheng Lin, Szuya Liao
  • Patent number: 12243359
    Abstract: According to one aspect, bandwidth associated with a vehicle communication network, such as a controller area network (CAN), is allocated by assigning priorities to systems in an autonomous vehicle which use the vehicle communication network to communicate with a vehicle control unit (VCU). Systems with high priority levels may exchange data or information with a VCU at substantially all times, while systems with lower priority levels may exchange data or information with the VCU substantially only when that data or information is requested or otherwise needed. A significant percentage of the bandwidth of the network may be allocated for the exchange of data between high priority systems and a VCU, while the remaining percentage of the bandwidth may be allocated for the exchange of data between lower priority systems and the VCU when needed. As a result, the bandwidth associated with the network may be used efficiently.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 4, 2025
    Assignee: NURO, INC.
    Inventor: Yin Wang
  • Publication number: 20250071964
    Abstract: In an embodiment, a device includes: a first transistor including a first gate structure; a second transistor including a second gate structure, the second gate structure disposed above and coupled to the first gate structure; a third gate structure; a fourth gate structure, the fourth gate structure disposed above and coupled to the third gate structure; a gate isolation region between the first gate structure and the third gate structure, the gate isolation region disposed between the second gate structure and the fourth gate structure; and a cross-coupling contact extending beneath the gate isolation region, the first gate structure, and the third gate structure, the cross-coupling contact coupled to the first gate structure.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Inventors: Tsung-Kai Chiu, Ting-Yun Wu, Cheng-Yin Wang, Szuya Liao
  • Publication number: 20250052670
    Abstract: Disclosed is a portable instrument for measuring gas concentration. A laser unit provides a laser beam required for laser spectral absorption. An optical unit includes a gas absorption cell (100). The gas absorption cell (100) includes a first reflective mirror (110), a second reflective mirror (120) and a cell tube (130), the first reflective mirror (110) and the second reflective mirror (120) are respectively connected to opposite ends of the cell tube (130). When the laser unit emits a laser beam, an optical path is formed between the first reflective mirror (110) and the second reflective mirror (120) within the cell tube (130). A heat recovery unit recycles heat generated by an electronic system unit (200) to the optical unit.
    Type: Application
    Filed: July 23, 2024
    Publication date: February 13, 2025
    Inventors: Yin WANG, Ting-jung LIN, Junhui ZENG, Jianwu ZHENG, Zhimei LIU
  • Publication number: 20250056648
    Abstract: Methods and systems for dynamic network keep-alive are described. In one embodiment, the method comprises establishing a link with an access point, determining a client station time interval and iteratively adjusting the duration of the client station time interval to approximate the access point time interval until the client station time interval is a close approximation of the access point time interval, thereby performing the keep-alive process at an efficient manner.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 13, 2025
    Applicant: Beken Corporation
    Inventors: Qiang SUN, Xiangdong WANG, Yin WANG, Xueli LYU
  • Publication number: 20250006254
    Abstract: A semiconductor device includes a first memory cell and a second memory cell. The first memory cell is configured to store a first data bit at a first node when the first memory cell is turned on. The second memory cell is configured to store the first data bit when the first memory cell is turned off. The first memory cell comprises a first switch coupled to the first node, and the first switch is configured to transmit the first data bit to the second memory cell, and configured to be turned off when the first memory cell is turned off.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Xiang YOU, Cheng-Yin WANG, Szuya LIAO
  • Publication number: 20250006815
    Abstract: A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kao-Cheng LIN, Cheng-Yin WANG, Yen Lin CHUNG, Wei Min CHAN, Yen-Huei CHEN
  • Publication number: 20240416590
    Abstract: A composite manufacturing method based on powder bed and five-axis additive and subtractive materials includes model Preprocessing: processing model adaptive compensation based on a design model and repairing the model after model compensation to obtain an additive model; decomposition and reconstruction: decomposing the additive model to obtain multiple sub-models that can plan the internal surface tool path at one time, and then processing additive manufacturing and CNC machining alternately for the sub-models according to the build sequence until composite manufacturing of all sub-models is completed; and post-processing: removing support structure and milling outer surface of the part after composite manufacturing of all sub-models is completed, in addition, after the influence of the powder bed and support is removed, reprocessing a non-machined part of internal structure to obtain a final required part.
    Type: Application
    Filed: August 7, 2023
    Publication date: December 19, 2024
    Inventors: Qi ZHANG, Yin WANG, Yukai CHEN, Yu LU, Junyao WANG, Bin HAN
  • Publication number: 20240385399
    Abstract: A connector module capable of transmitting display data signals includes first and second light-emitting devices, a module connector including first and second terminals, and first and second optical transceivers respectively including at least one electrical-optical converting circuit and at least one optical-electrical converting circuit. One of the at least one electrical-optical converting circuit of the first optical transceiver is electrically coupled to the first light-emitting device and the first terminal, and one of the at least one electrical-optical converting circuit of the second optical transceiver is electrically coupled to the second light-emitting device and the second terminal. A portion of the at least one optical-electrical converting circuit of the first optical transceiver is electrically isolated to any optoelectronic device and the module connector.
    Type: Application
    Filed: March 20, 2024
    Publication date: November 21, 2024
    Inventors: Chang-Lin Hsieh, Che-Fu Liang, Shih-Jou Huang, Kun-Yin Wang
  • Publication number: 20240381610
    Abstract: The first semiconductor layer and the second semiconductor layer are above the first semiconductor layer, in which the first and second semiconductor layers are vertically spaced apart from each other. The first and second source/drain epitaxial features are respectively on first and second sides of the first semiconductor layer. The third and fourth source/drain epitaxial features are respectively on first and second sides of the second semiconductor layer and above the first source/drain epitaxial feature. The first, third, and fourth source/drain epitaxial features have a first conductive type, and the second source/drain epitaxial feature has a second conductive type opposite to the first conductive type.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yin WANG, Wei-Xiang YOU, Kao-Cheng LIN, Jui-Chien HUANG, Szuya LIAO
  • Publication number: 20240373762
    Abstract: A device comprises a semiconductor-superconductor hybrid structure comprising a semiconductor component and a superconductor component, the superconductor component comprising a layer of aluminium; at least one conductive lead in tunnelling communication with the semiconductor-superconductor hybrid structure; and a tunnel barrier arranged between the semiconductor-superconductor hybrid structure and the at least one conductive lead. The conductive lead is arranged over the superconductor component such that the superconductor component shields the semiconductor component from the conductive lead. The tunnel barrier is arranged between the superconductor component and the at least one conductive lead. The tunnel barrier consists of a native aluminium oxide layer formed integrally to the superconductor component. Forming the tunnel barrier integrally to the superconductor component provides a high-quality dielectric barrier between the conductive lead and the semiconductor-superconductor hybrid structure.
    Type: Application
    Filed: September 1, 2021
    Publication date: November 7, 2024
    Inventors: Leonardus P. Kouwenhoven, Ji-Yin WANG, Vukan LEVAJAC, Mathilde Flore LEMANG
  • Publication number: 20240347131
    Abstract: A cancer detection model and a construction method therefor, and a reagent kit, relating to the technical field of cancer detection. The method comprises: performing whole genome sequencing on plasma free DNA to mine nucleosome distribution features, terminal sequence features, and fragment size distribution features that can be applied to cancer detection; constructing classification models of the three indicators to obtain prediction scores of each indicator for a sample; then integrating these scores using a logistic regression model, and adding copy number variation feature information to obtain an ultimate classification and prediction model.
    Type: Application
    Filed: March 8, 2022
    Publication date: October 17, 2024
    Applicant: BERRY ONCOLOGY CO., LTD.
    Inventors: Qingzheng ZHANG, Lu ZHENG, Fuming SUN, Jian BAI, Yin WANG, Xiaoling LI, Lin WU
  • Publication number: 20240340687
    Abstract: Aspects of the present disclosure are directed to dynamic adjustment of load-balancing weights across multiple network transport interfaces in a network, informed in part by Quality of Service (QoS) metrics. In one aspect, a method includes determining one or more metrics based on one or more Software-defined Wide Area Network (SDWAN) session level throughput and SDWAN session loss through one or more tunnels; generating a Quality of Service (QoS) SDWAN session level shape rate per tunnel based on the one or more metrics; and dynamically adjusting an SDWAN forwarding load-balance weight for each of the one or more tunnels based on the QoS SDWAN session level shape rate.
    Type: Application
    Filed: July 25, 2023
    Publication date: October 10, 2024
    Inventors: Tony Shen, Hongbo Xia, Alan Xiao-rong Wang, Yin Wang
  • Publication number: 20240315391
    Abstract: Disclosed are a shoe midsole and a shoe. The shoe midsole includes a midsole body. The midsole body is provided with a plurality of followers, the followers include segmentation portions and support bodies. The segmentation portions are distributed adjacent to the support bodies. At least one segmentation portion runs through the midsole body in a width direction of the midsole body. In the shoe midsole and the shoe of the present application, through adjacent distribution of the segmentation portion and the support body, the support body has a space that inclines toward the peripheral segmentation portion. When a shoe sole is stressed during exercise, the support body is subjected to an impact force to incline toward the peripheral segmentation portion along a stressed direction. A ground impacting force is absorbed through passive compression deformation of the support body, such that effects of cushioning and shock absorption are realized.
    Type: Application
    Filed: January 18, 2024
    Publication date: September 26, 2024
    Applicants: SANLIUYIDU (CHINA) CO., LTD., SANLIUYIDU (FUJIAN) SPORTS GOODS CO., LTD.
    Inventors: Huilian DAI, Shutao WEI, Siqi LIU, Tao ZHOU, Yin WANG
  • Patent number: 12101851
    Abstract: The present disclosure provides methods and network function nodes for managing a communication of contents for a first UE. The method includes retrieving subscription data for the first UE from a third NF node, the subscription data indicating an identifier of a second UE which is a target of the contents for the first UE, transmitting the contents and the identifier of the second UE to a second NF node, receiving a message built with the contents from the second NF node, and transmitting the message to the second UE. The present disclosure further provides corresponding computer readable medium.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 24, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Zhiwei Qu, Yin Wang
  • Patent number: 12097865
    Abstract: According to one aspect, a method includes obtaining, at a first unit, a first signal, and storing an indication of an arrival time of the first signal in a register of the first unit. The method also includes obtaining a digital signal to be provided to a controller area network (CAN) circuit system, the CAN circuit system being included in the first unit, adding the indication to the digital signal, wherein adding the indication to the digital signal creates an updated digital signal, and providing the updated digital signal to the CAN circuit system.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: September 24, 2024
    Assignee: NURO, INC.
    Inventors: Yin Wang, Paul Michael White, Matthew Jeremy Sarett, William Campbell Martin
  • Publication number: 20240314998
    Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Cheng-Yin WANG, Szuya LIAO, Tsung-Kai CHIU, Shao-Tse HUANG, Ting-Yun WU, Wen-Yuan CHEN
  • Publication number: 20240282364
    Abstract: An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.
    Type: Application
    Filed: July 26, 2023
    Publication date: August 22, 2024
    Inventors: Wei-Xiang YOU, Szuya LIAO, Cheng-Yin WANG
  • Publication number: 20240257867
    Abstract: Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Wei-Xiang YOU, Wen-Yuan CHEN, Cheng-Yin WANG, Szuya LIAO