Abstract: A cable including a first insulating layer, a twisted pair, a ground structure, and at least one conducting element is provided. The twisted pair is disposed in the first insulating layer and includes two signal wires, wherein the two signal wires are intertwisted to each other. The ground structure is disposed at the first insulating layer. The conducting element includes a main body portion and at least one extending portion. The main body portion is disposed in the twisted pair to be surrounded by the two signal wires. The extending portion is connected to the main body portion and grounded to the ground structure.

Abstract: The present invention provides a method for treating and preventing neurodegenerative diseases, comprising administering an effective amount of a compound isolated from Antrodia camphorate, represented by formula (I), to a subject in need thereof; wherein R1 is a hydrogen atom or an acetyl group, and R2 is

Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes an embedded cavity, the perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask dam. The solder mask dam defines cavity dimensions and prevents prepreg resin flow into the cavity during lamination.

Abstract: A PCB having multiple stacked layers laminated together. The laminated stack includes regular flow prepreg and includes a recessed cavity, a bottom perimeter of which is formed by a photo definable, or photo imageable, polymer structure, such as a solder mask frame, and a protective film. The solder mask frame and protective film protect inner core circuitry at the bottom of the cavity during the fabrication process, as well as enable the use of regular flow prepreg in the laminated stack.

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are covered by a coverlay material and the covered inner core circuitry is exposed from the remaining layers of the PCB. The PCB having covered inner core circuitry is formed using a dummy core plus coverlay process. The select inner core circuitry is part of an inner core. The inner core corresponding to the covered inner core circuitry forms a flexible PCB portion. The flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the flexible PCB portion and the remaining rigid PCB portion.

Abstract: A method of and a device for dissipating/transferring heat through one or more solid vias and embedded coins are disclosed. The method and device disclosed herein can be used to transfer heat for a High Density Interconnect (HDI) board.

Abstract: A printed circuit board (PCB) has multiple layers, where select portions of inner layer circuitry, referred to as inner core circuitry, are exposed from the remaining layers. The PCB having an exposed inner core circuitry is formed using a dummy core plus plating resist process. The select inner core circuitry is part of an inner core. The inner core corresponding to the exposed inner core circuitry forms a semi-flexible PCB portion. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The inner core is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.

Abstract: A printed circuit board (PCB) has multiple layers, where select portions of one or more conductive layers, referred to as core circuitry, form a semi-flexible PCB portion that is protected by an exposed prepreg layer. The semi-flexible PCB portion having an exposed prepreg layer is formed using a dummy core process that leaves the exposed prepreg layer smooth and undamaged. The core circuitry is part of a core structure. The semi-flexible PCB portion is an extension of the remaining adjacent multiple layer PCB. The remaining portion of the multiple layer PCB is rigid. The core structure is common to both the semi-flexible PCB portion and the remaining rigid PCB portion.

Abstract: A cable including a first insulating layer, a twisted pair, a ground structure, and at least one conducting element is provided. The twisted pair is disposed in the first insulating layer and includes two signal wires, wherein the two signal wires are intertwisted to each other. The ground structure is disposed at the first insulating layer. The conducting element includes a main body portion and at least one extending portion. The main body portion is disposed in the twisted pair to be surrounded by the two signal wires. The extending portion is connected to the main body portion and grounded to the ground structure.

Abstract: A display circuit includes a graphics display unit for generating a graphics display signal; a first BIOS and a second BIOS electrically connected to the graphics display unit, and respectively storing a first BIOS program code and a second BIOS program code; a BIOS switch electrically for enabling one of the first BIOS and the second BIOS and disabling the other; an output switch electrically connected to the graphics display unit; a first output port and a second output port electrically connected to the output switch. When the graphics display unit loads the first BIOS program code, the output switch is switched to electrically connect the first output port to the graphics display unit; when the graphics display unit loads the second BIOS program code, the output switch is switched to electrically connect the second output port to the graphics display unit.

Abstract: A bioprinter and methods of using the bioprinter. The bioprinter permits selective three-dimensional movement of multiple nozzle assemblies during operation of the bioprinter. The bioprinter can be used to produce scaffold-free tissue constructs having a plurality of cellular elements interspersed among a semi-permeable vascular network. The bioprinter can also be used to print a tissue construct directly onto a tissue defect of a subject. The bioprinter can be provided as part of a bioprinting system that includes a scanner for imaging the tissue defect.

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract: A common mode filter includes a ground element, a transmission line pair and an extension element, which are disposed in first to third signal layers of a circuit board. The ground element includes a ground portion and a first ground line electrically connected with each other. The first ground line is disposed in a slot of the ground portion, and extends from a bottom portion to an opening of the slot. An orthogonal projection of the transmission line pair on the first signal layer is partially overlapped with an orthogonal projection of the ground portion on the first signal layer. The orthogonal projection of the transmission line pair on the first signal layer is not overlapped with an orthogonal projection of the first ground line on the first signal layer. The extension element is electrically connected to the first ground line through at least one conductive via.

Abstract: A cable structure includes isolation layers, a first signal wire, a second signal wire, a first ground wire, a second ground wire, a first conductor, and a second conductor. These signal and ground wires are parallel along a first direction and between the isolation layers. These signal wires are adjacent, and the ground wires are respectively at outer sides of these signal wires. The first conductor is on at least one of the isolation layers along a second direction orthogonal to the first direction and is electrically connected to the first and second ground wires. The second conductor is on an outer surface of at least one of the second isolation layers along the first direction and is electrically connected to the first conductor. The second conductor is symmetrical based on a central line between the first and second signal wires.

Abstract: A gate driving apparatus is disclosed. The gate driving apparatus includes a first gate driving chip and N second gate driving chips, wherein N is positive integer. The first gate driving chip has a first input pin and a first current output pin. The first gate driving chip receives a reference electrical signal by the first input pin, and generates a reference current according to the reference electrical signal. The first current output pin is used for outputting the reference current. Each of the second gate driving chips has a current input pin for receiving the reference current and a second current output pin for outputting the reference current. The first gate driving chip and the second gate driving chips generate at least a first output signal and at least N second output signals according to the reference current.

Abstract: A display circuit includes a graphics display unit for generating a graphics display signal; a first BIOS and a second BIOS electrically connected to the graphics display unit, and respectively storing a first BIOS program code and a second BIOS program code; a BIOS switch electrically for enabling one of the first BIOS and the second BIOS and disabling the other; an output switch electrically connected to the graphics display unit; a first output port and a second output port electrically connected to the output switch. When the graphics display unit loads the first BIOS program code, the output switch is switched to electrically connect the first output port to the graphics display unit; when the graphics display unit loads the second BIOS program code, the output switch is switched to electrically connect the second output port to the graphics display unit.

Abstract: A common mode filter includes a ground element, a transmission line pair and an extension element, which are disposed in first to third signal layers of a circuit board. The ground element includes a ground portion and a first ground line electrically connected with each other. The first ground line is disposed in a slot of the ground portion, and extends from a bottom portion to an opening of the slot. An orthogonal projection of the transmission line pair on the first signal layer is partially overlapped with an orthogonal projection of the ground portion on the first signal layer. The orthogonal projection of the transmission line pair on the first signal layer is not overlapped with an orthogonal projection of the first ground line on the first signal layer. The extension element is electrically connected to the first ground line through at least one conductive via.

Abstract: An input system is applicable to a computer. The input system includes a wireless operating apparatus and a portable electronic apparatus. The wireless operating apparatus includes an operating unit and a wireless transmitting unit. The operating unit generates data information. The wireless transmitting unit is electrically connected to the operating unit, and is used to transmit the data information in a wireless manner. The portable electronic apparatus includes a display device, a wireless receiving unit, and a data transmission port. The wireless receiving unit is electrically connected to the display device and the data transmission port, and is used to receive the data information from the wireless transmitting unit of the wireless operating apparatus. The data transmission port transmits the data information to the computer by using a data transmission line. Therefore, a portable electronic apparatus is used as a wireless transceiver.