Patents by Inventor Ying An

Ying An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11986774
    Abstract: Disclosed are methods of preparing a porous ceramic support for an ultra-thin enzyme-assisted membrane, and a new membrane that can be used for gas filtration purposes to remove/separate carbon dioxide or other gases from a gas mixture such as those from power production or enhanced oil recovery or fuel production or air, and recycle/collect/utilize carbon dioxide. In some embodiments, a method may include blocking the pores of a porous substrate with a removable medium, and polishing the surface, coating a silica sol-gel solution onto the support, and removing the blocking medium and sol-gel surfactant to leave a well-confined porous structure.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: May 21, 2024
    Assignee: Memzyme, LLC
    Inventors: Caroline Rempe, Ying-Bing Jiang, Yongqian Gao, Jimin Guo
  • Patent number: 11989823
    Abstract: The invention discloses a method for rendering on the basis of hemispherical orthogonal function, the method comprising the following steps: selecting rendering fragments and establishing a local coordinate system; acquiring a bidirectional reflectance distribution function of a material; if global illumination is an orthogonal function, determining a rotation matrix of an orthogonal function coefficient according to the rotation angles of the global coordinate system and the local coordinate system, and calculating a local orthogonal function illumination coefficient; converting the local orthogonal function illumination coefficient into a hemispherical orthogonal function illumination coefficient; sampling to obtain the spatial distribution of a bidirectional reflection distribution function of a rendered material; obtaining a hemispherical orthogonal function of the bidirectional reflection distribution function of the rendered material; and using the dot product of a hemispherical orthogonal function coef
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 21, 2024
    Assignee: NANJING INSTITUTE OF ASTRONOMICAL OPTICS & TECHNOLOGY, NATIONAL ASTRONOMICAL OBSERVATORIES, CAS
    Inventors: Yi Zheng, Kai Wei, Bin Liang, Ying Li, Changpeng Ding
  • Publication number: 20240162955
    Abstract: Various embodiments herein are directed to beamforming associated with multiple-input multiple-output (MIMO) modes in open radio access network (O-RAN) systems. In one embodiment, an apparatus comprises: memory to store beamforming configuration information associated with a plurality MIMO modes; and processing circuitry, coupled with the memory to: retrieve the beamforming configuration information from the memory; request, based on the beamforming configuration information, measurements associated with the plurality of MIMO modes; receive the measurements associated with the plurality of MIMO modes; and based on the received measurements, train an artificial intelligence/machine learning (AI/ML) model that is to predict relative beamforming performance between the plurality of MIMO modes.
    Type: Application
    Filed: July 12, 2022
    Publication date: May 16, 2024
    Inventors: Nicholas Whinnett, Dawei Ying, Bishwarup Mondal, Jan Schreck, Jaemin Han, Leifeng Ruan, Jianli Sun
  • Publication number: 20240157437
    Abstract: A method produces tantalum powder. The method includes: (1) uniformly mixing a tantalum powder raw material, metal magnesium and at least one alkali metal and/or alkaline earth metal halide, loading the mixture into a container, and putting the container in a furnace; (2) raising the temperature of the furnace to 600-1200° C. in the presence of inert gas, and soaking; (3) at the end of soaking, lowering the temperature of the furnace to 600-800° C., vacuumizing the interior of the furnace to 10 Pa or less, soaking under the negative pressure so that the excessive metal is separated; (4) thereafter, raising the temperature of the furnace to 750-1200° C. in the presence of inert gas, and soaking so that the tantalum powder is sintered in the molten salt after oxygen reduction; (5) then cooling to room temperature and passivating to obtain a mixed material containing halide and tantalum powder; and (6) separating the tantalum powder from the resulting mixture.
    Type: Application
    Filed: August 24, 2022
    Publication date: May 16, 2024
    Inventors: Yuewei Cheng, Hongyuan Liang, Shun Guo, Jinfeng Zheng, Haiyan Ma, Jingyi Zuo, Li Zhang, Hongjie Qin, Tong Liu, Ying Wang
  • Publication number: 20240162375
    Abstract: A light-emitting device comprises a first semiconductor layer and a semiconductor mesa formed on the first semiconductor layer, wherein the first semiconductor layer comprises a first sidewall and a first semiconductor layer first surface surrounding the semiconductor mesa, and the semiconductor mesa comprises a second sidewall; and a first reflective structure comprising a first reflective portion covering the first sidewall and a second reflective portion covering the second sidewall, wherein the first reflective portion and the second reflective portion are connected to form a first reflective structure outer opening to expose the first semiconductor layer first surface in a top view of the light-emitting device.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 16, 2024
    Inventors: Heng-Ying CHO, Yong-Yang CHEN, Yu-Ling LIN, Wei-Chen TSAO
  • Publication number: 20240164223
    Abstract: A method includes forming a dielectric layer over a substrate, the dielectric layer having a top surface; etching an opening in the dielectric layer; forming a bottom electrode within the opening, the bottom electrode including a barrier layer; forming a phase-change material (PCM) layer within the opening and on the bottom electrode, wherein a top surface of the PCM layer is level with or below the top surface of the dielectric layer; and forming a top electrode on the PCM layer.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Inventors: Tung Ying Lee, Yu Chao Lin, Shao-Ming Yu
  • Publication number: 20240162217
    Abstract: A semiconductor device includes a substrate, two first voltage-to-current converters and two second voltage-to-current converters. The substrate includes four layout regions arranged in an array having a plurality of columns and a plurality of rows. The array is line-symmetrical with respect to a first axis and line-symmetrical with respect to a second axis, wherein the first axis perpendicularly intersects the second axis at an array center point of the array. The two first voltage-to-current converters are respectively arranged in two of the four layout regions, wherein layouts of the two first voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point. The two second voltage-to-current converters are respectively arranged in the other two of the four layout regions, wherein layouts of the two second voltage-to-current converters on the substrate are point-symmetrical with respect to the array center point.
    Type: Application
    Filed: September 26, 2023
    Publication date: May 16, 2024
    Inventors: Tzu-Chieh WEI, Chun Ying KAN
  • Publication number: 20240163223
    Abstract: The present invention relates to a method (100) for network-on-chip arbitration. The method (100) comprises the steps of receiving input from a user via user interface and selecting a plurality of flits from a plurality of ingress into a plurality of virtual channels followed by selecting the flits from the virtual channels into a plurality of egress based on the input from the user. The selection of the flits into the virtual channels and the egress characterized by the steps of computing default and elevated bandwidths of the virtual channels, computing default and elevated weights of the virtual channels based on the default and elevated bandwidths and generating a weightage lookup table using the default and elevated weights to perform arbitration weightage lookup for the flits with default and elevated priority levels for selecting the flits into the virtual channels and the egress, wherein the flits from the different ingress comprise different default and elevated weight.
    Type: Application
    Filed: December 13, 2022
    Publication date: May 16, 2024
    Applicant: SKYECHIP SDN BHD
    Inventors: YEONG TAT LIEW, YU YING ONG, SOON CHIEH LIM, WENG LI LEOW, CHEE HAK TEH
  • Publication number: 20240160828
    Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Ke-Ying SU, Jon-Hsu HO, Ke-Wei SU, Liang-Yi CHEN, Wen-Hsing HSIEH, Wen-Koi LAI, Keng-Hua KUO, KuoPei LU, Lester CHANG, Ze-Ming WU
  • Publication number: 20240157171
    Abstract: A tumor radiotherapy planning design method and apparatus, an electronic device, and a computer storage medium are provided, including: obtaining a current optimization parameter vector set, and calculating a current cost function value; randomly correcting the current optimization parameter vector set to generate alternative optimization parameter vector sets; then performing planning parameter optimization, and calculating corresponding total cost function values; determining current optimal or suboptimal alternative optimization parameter vector sets according to the total cost function values, sampling to update the current optimization parameter vector set and the current cost function value according to the total cost function values of the current alternative optimization parameter vector sets, and then performing an iteration repeatedly until a convergence condition is satisfied; and outputting an optimal optimization parameter vector set after the iteration, determining planning parameters, and calcu
    Type: Application
    Filed: July 18, 2023
    Publication date: May 16, 2024
    Inventors: Xiaoyu Yang, Yuqian Zhao, Zhen Yang, rui Wei, Ying Cao, Shuzhou Li, Qigang Shao, Du Tang, Zhao Peng
  • Publication number: 20240161465
    Abstract: An image processing method including obtaining a fake template sample group comprising a first source image, a real labeled image, and a fake template image, inputting the fake template image into an identity swapping model to obtain a first identity swapping image of the fake template image, obtaining a fake labeled sample group comprising a second source image, a real template image, and a fake labeled image, the fake labeled image being based on identity swapping processing of the real template image, inputting the real template image into the identity swapping model to obtain a second identity swapping image of the real template image, and training the identity swapping model based on the fake template sample group, the first identity swapping image, the fake labeled sample group, and the second identity swapping image to generate a trained identity swapping model.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 16, 2024
    Applicant: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED.
    Inventors: Keke HE, Junwei ZHU, Ying TAI, Chengjie WANG
  • Publication number: 20240162216
    Abstract: A semiconductor device includes a substrate, two first voltage-to-current converters, two second voltage-to-current converters and two third voltage-to-current converters. The substrate includes six layout regions arranged as an array having a plurality of columns and a plurality of rows, the array is line-symmetrical with respect to a first axis and a second axis which are perpendicularly intersected at an array center point of the array. The two first voltage-to-current converters, the two second voltage-to-current converters and the two third voltage-to-current converters are respectively arranged in the six layout regions. With respect to the array center point, layouts of the two first voltage-to-current converters are point-symmetrical, layouts of the two second voltage-to-current converters are point-symmetrical, and layouts of the two third voltage-to-current converters are point-symmetrical.
    Type: Application
    Filed: September 26, 2023
    Publication date: May 16, 2024
    Inventors: Tzu-Chieh WEI, Chun Ying KAN
  • Publication number: 20240156683
    Abstract: Disclosed is a reusable actuator for use with a drug container including a stopper comprising a container having a closed end, an open end, and a sidewall extending therebetween in a longitudinal direction, an electrode disposed inside the container for use in generating a gas, an actuating element disposed at and closing the open end of the container, the actuating element and the container defining an actuator interior, wherein the actuating element is movable relative to the container in the longitudinal direction by a gas pressure of the gas in the actuator interior, such that the actuating element applies a force to the stopper to cause a drug delivery from the drug container, and a retracting mechanism for use in removing the gas to assist the actuating element's retraction for reuse.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Applicant: MicroMED Co., Ltd.
    Inventors: Chia-Chi FENG, Po-Ying LI, Hong Jun YEH, Kuang-Hsiang CHENG
  • Publication number: 20240162005
    Abstract: Systems and methods for increasing peak ion energy with a low angular spread of ions are described. In one of the systems, multiple radio frequency (RF) generators that are coupled to an upper electrode associated with a plasma chamber are operated in two different states, such as two different frequency levels, for pulsing of the RF generators. The pulsing of the RF generators facilitates a transfer of ion energy during one of the states to another one of the states for increasing ion energy during the other state to further increase a rate of processing a substrate.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Inventors: Juline Shoeb, Ying Wu, Alex Paterson
  • Publication number: 20240161107
    Abstract: NFT transaction method and system relating to biological feature include: receiving, at a biological asset module of an NFT transaction system, a biological cell or tissue from a provider; obtaining, at the biological asset module, the biological feature from the biological cell or tissue; producing, at a digital asset module of the NFT transaction system, a digital creation based on the biological feature; minting, at the digital asset module, a to-be-traded NFT corresponding to the digital creation; evaluating and updating, at a transaction module of the NFT transaction system, a market price of the to-be-traded NFT based on a market condition of the biological feature; and conducting a first transaction matchmaking for the to-be-traded NFT on a virtual transaction platform based on the market price.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Inventors: TSUNG-CHI CHEN, YING-CHEN YANG
  • Publication number: 20240162141
    Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.
    Type: Application
    Filed: January 22, 2024
    Publication date: May 16, 2024
    Inventors: Ehren MANNEBACH, Aaron LILAK, Hui Jae YOO, Patrick MORROW, Anh PHAN, Willy RACHMADY, Cheng-Ying HUANG, Gilbert DEWEY, Rishabh MEHANDRU
  • Publication number: 20240163947
    Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: Cheng-Ying WU, Wei-Wen LIN, Shu-Min CHENG, Hui-Ping TSENG, Chi-Han HUANG, Chih-Chun KUO, Yang-Hung PENG, Hao-Hua KANG
  • Publication number: 20240163231
    Abstract: An electronic apparatus includes a processing unit, a buffer memory and a buffer manager. The buffer memory includes some packet buffer slots. Each of the packet buffer slots aligns to a packet size. The buffer manager includes a cache for registering available pointers. Each of the available pointers is configured to mark a start address of one of the packet buffer slots. The buffer manager is configured to monitor an available pointer count of the available pointers. When the processing unit transmits an allocation request to the buffer manager and the available count is enough, the buffer manager obtains one available pointer from the cache and integrates the one available pointer and the available pointer count into an allocation response, which is sent to the processing unit.
    Type: Application
    Filed: October 4, 2023
    Publication date: May 16, 2024
    Inventors: Ying-Sheng TSAI, Jen-Che TSAI, Shiao-Yang WU
  • Publication number: 20240162183
    Abstract: In some embodiments, the present disclosure relates to an integrated chip including a substrate and a first die disposed over the substrate. A first plurality of die stopper bumps are disposed along a backside of the first die. The first plurality of die stopper bumps directly contact the backside of the first die, and the first plurality of die stopper bumps are arranged as a plurality of groups of die stopper bumps. A plurality of adhesive structures are also present. Each of the plurality of adhesive structures surrounds a corresponding group of the plurality of groups of die stopper bumps.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Inventors: Wei-Jhih Mao, Kuei-Sung Chang, Shang-Ying Tsai
  • Publication number: 20240158810
    Abstract: The disclosure features compositions and methods for ameliorating cognitive impairments associated with neuropsychiatric disorders, particularly those associated with anterodorsal (AD) thalamus hyperexcitability in the brain of a subject. Various embodiments of the disclosure provide for personalized and targeted therapeutic approaches for screening, diagnosing, preventing, and treating cognitive impairments and neuropsychiatric disorders.
    Type: Application
    Filed: December 22, 2023
    Publication date: May 16, 2024
    Applicants: The Broad Institute, Inc., Massachusetts Institute of Technology
    Inventors: Guoping FENG, Dheeraj ROY, Ying ZHANG