Patents by Inventor Ying An

Ying An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230416839
    Abstract: A method for detecting a human microsatellite instability (MSI) site involves a primer, a probe, and a detection system used for detecting an MSI. The present method and kit thereof may be used for detecting whether MSI-H is present in a tumor patient, and provide medication guidance or provide risk assessment guidance according to a detection result.
    Type: Application
    Filed: January 17, 2022
    Publication date: December 28, 2023
    Inventors: Xin HUANG, Ying JIANG
  • Publication number: 20230420460
    Abstract: An integrated circuit structure includes a device layer including an upper device above a lower device. The upper device includes an upper source or drain region, and an upper source or drain contact coupled to the upper source or drain region. The lower device includes a lower source or drain region. A first conductive feature is below the device layer, where the first conductive feature is coupled to the lower source or drain region. A second conductive feature vertically extends through the device layer. In an example, the second conductive feature is to couple (i) the first conductive feature below the device layer and (ii) an interconnect structure above the device layer. Thus, the first and second conductive features facilitate a connection between the interconnect structure on the frontside of the integrated circuit and the lower source or drain region towards the backside of the integrated circuit.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Patrick Morrow, Quan Shi, Rohit Galatage, Nicole K. Thomas, Munzarin F. Qayyum, Jami A. Wiedemer, Gilbert Dewey, Mauro J. Kobrinsky, Marko Radosavljevic, Jack T. Kavalieros
  • Publication number: 20230416329
    Abstract: Provided are a polypeptide containing disulfide bonds and capable of inhibiting activity of serine protease, and a use thereof, relating to three types of linear polypeptide molecules, respectively capable of inhibiting the activity of small intestine protein metabolic enzymes such as trypsin, chymotrypsin, and elastase. Said polypeptide molecules may be broadly fused to another polypeptide or protein drug capable of treating a disease, so as to form a hybrid peptide. The hybrid peptide may inhibit the degradation of metabolic enzymes to improve the stability of a peptide or protein drug for treating a disease, such that the curative effect of direct injection administration is improved, while also facilitating direct administration absorption of the polypeptide or protein drug in the small intestine, and implementing oral administration of the protein polypeptide drug.
    Type: Application
    Filed: November 29, 2021
    Publication date: December 28, 2023
    Inventors: Wei WANG, Zhufang SHEN, Minzhi LIU, Caina LI, Sujuan SUN, Ying MA, Hui CAO, Haijing ZHANG, Yan YANG, Lianqiu WU
  • Publication number: 20230420895
    Abstract: An improved modularized socket structure comprises: a main socket module, first, second and third polar main jacks are formed on a main conductive component of the module; at least one expansion socket module, first, second and third polar expansion jacks are formed on an expansion conductive component of the module; a sub-socket module, first, second and third polar sub-jacks are formed on a sub-conductive component of the module; and an expansion conductive plate set comprising first, second and third conductive plates, the first conductive plate has first extension portions inserted into first polar main jack, first polar expansion jack and first polar sub-jack, the second conductive plate has second extension portions inserted into second polar main jack, second polar expansion jack and second polar sub-jack, and the third conductive plate has third extension portions inserted into third polar main jack, third polar expansion jack and third polar sub-jack.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 28, 2023
    Inventors: YUEH-YING LEE, YUEH-HUI LEE
  • Publication number: 20230416265
    Abstract: tion of heme oxygenase 1 (HO-1), in particular porphyrin, chlorin, bacteriochlorin or isobacteriochlorin compounds of formula I as defined herein having a tetrapyrrole or reduced tetrapyrrole backbone and a fluorophore. Such compounds can be used in the detection of HO-1 in vivo, ex vivo and in vitro, and can also be used in methods of diagnosis and as research reagents.
    Type: Application
    Filed: November 12, 2021
    Publication date: December 28, 2023
    Inventors: Joseph James BOYLE, Nicholas J. LONG, Edward R.H. WALTER, Ying GE, Justin C. MASON
  • Publication number: 20230420338
    Abstract: Techniques for heat sinks and cold plates for compute systems are disclosed. In one embodiment, a heat sink includes two sub-heat sinks that are mechanically connected but thermally isolated. The two sub-heat sinks can independently cool different dies on the same integrated circuit component. In another embodiment, a system includes an integrated circuit component that is cooled by a first water block and a second water block. The first water block forms a loop with a gap in it, and the second water block has a pedestal that extends through the gap in the first water block to contact the integrated circuit component. The first water block and the second water block can independently cool different dies on the same integrated circuit component.
    Type: Application
    Filed: March 6, 2021
    Publication date: December 28, 2023
    Inventors: Prabhakar SUBRAHMANYAM, Tong Wa CHAO, Ying-Feng PANG, Yi XIA, Rahima K. MOHAMMED, Victor P. POLYANKO, Ridvan A. SAHAN, Guangying ZHANG, Guoliang YING, Chuanlou WANG, Jun LU, Liguang DU, Peng WEI, Xiang QUE
  • Patent number: 11854966
    Abstract: A method of manufacturing a semiconductor device includes forming via structures in a first via layer over a transistor layer, the forming the via structures in the first via layer including forming a first via structure in the first via layer, the first via structure being included in a first deep via arrangement; forming conductive segments in a first metallization layer over the first via layer, the forming the conductive segments in the first metallization layer including forming M_1st routing segments at least a majority of which, relative to a first direction, have corresponding long axes with lengths which at least equal if not exceed a first permissible minimum value for routing segments in the first metallization layer; and forming an M_1st interconnection segment having a long axis which is less than the first permissible minimum value, the M_1st interconnection segment being included in the first deep via arrangement.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Pen Guo, Chien-Ying Chen, Li-Chun Tien, Lee-Chung Lu
  • Patent number: 11855155
    Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xusheng Wu, Chang-Miao Liu, Ying-Keung Leung, Huiling Shang, Youbo Lin
  • Patent number: 11855232
    Abstract: A semiconductor package is provided. The semiconductor package includes a heat dissipation substrate including a first conductive through-via embedded therein; a sensor die disposed on the heat dissipation substrate; an insulating encapsulant laterally encapsulating the sensor die; a second conductive through-via penetrating through the insulating encapsulant; and a first redistribution structure and a second redistribution structure disposed on opposite sides of the heat dissipation substrate. The second conductive through-via is in contact with the first conductive through-via. The sensor die is located between the second redistribution structure and the heat dissipation substrate. The second redistribution structure has a window allowing a sensing region of the sensor die receiving light. The first redistribution structure is electrically connected to the sensor die through the first conductive through-via, the second conductive through-via and the second redistribution structure.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chih-Hao Chang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
  • Patent number: 11856710
    Abstract: A method of manufacturing an electronic device including the following steps is provided herein. A plurality of first electronic components is provided. The plurality of first electronic components is transferred onto a plurality of pickup sites. An empty pickup site from the plurality of pickup sites may be figured out, wherein the plurality of first electronic components is absent at the empty pickup site. A second electronic component is transferred onto the empty pickup site. A target substrate is provided. The plurality of first electronic components and the second electronic component are transferred onto the target substrate.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Innolux Corporation
    Inventors: Kai Cheng, Fang-Ying Lin, Tsau-Hua Hsieh
  • Patent number: 11854968
    Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Sheng Chang, Chien-Ying Chen, Yao-Jen Yang
  • Patent number: 11856855
    Abstract: Provided are a thermal sensor and a manufacturing method thereof. The thermal sensor includes a transistor and a thermal sensing device. The thermal sensing device is disposed in a recess in a substrate and electrically connected to the transistor. The thermal sensing device includes a first dielectric layer, a metal silicide reflective layer, a second dielectric layer, and a thermal absorbing layer. The first dielectric layer is disposed on sidewalls and a bottom of the recess. The metal silicide reflective layer is disposed on the first dielectric layer located on the bottom of the recess. The second dielectric layer is disposed at a top of the recess. The thermal absorbing layer is disposed on the second dielectric layer.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: December 26, 2023
    Assignee: Nuvoton Technology Corporation
    Inventors: In-Shiang Chiu, Kuang-Chu Chen, Peng-Chan Hsiao, Han-Ying Liu
  • Patent number: 11855763
    Abstract: In NR networks with dynamic TDD operation, two types of cross-link interference (CLI) arise: UE-to-UE and TRP-to-TRP. UE-to-UE CLI measurement and reporting can assist the network in managing CLI. The problem is that, for a cell to be able to measure the CLI reference signal transmitted by UEs in another neighboring cell, the cell needs to know what CLI-RS transmission resources assigned to the UEs in the neighboring cells. Embodiments of the present disclosure provide systems and methods for the exchange of such information between cells. In some embodiments, for example, a gNB sends a request message to a neighboring gNB and the neighboring gNB sends back a response message that includes TDD DL/UL Configurations of its cells and a list of the resources assigned to its UEs for transmission of UE-to-UE CLI reference signal.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 26, 2023
    Assignee: Apple Inc.
    Inventors: Hassan Ghozlan, Dawei Ying, Qian Li, Geng Wu
  • Patent number: 11852888
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a first movable portion, a fixed portion, a first driving assembly, and a first guiding assembly. The first movable portion is used for connecting to a first optical element driving mechanism. The first optical element driving mechanism has a main axis that extends in a first direction. The first movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the first movable portion to move relative to the fixed portion. The first guiding assembly is used for guiding the movement of the fixed portion relative to the fixed portion.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: December 26, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Ya-Hsiu Wu, Ying-Jen Wang, Sin-Jhong Song
  • Patent number: 11852602
    Abstract: A liquid detection device and a method for manufacturing the same are provided. The liquid detection device includes: a substrate; a working electrode disposed on the substrate, wherein the working electrode includes a first metal portion and a first sensing portion, and the first sensing portion is disposed on the first metal portion; and a reference electrode disposed on the substrate.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: December 26, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Fuh-Tsang Wu, Yi-Hung Lin, Huei-Ying Chen
  • Patent number: 11856876
    Abstract: Semiconductor devices and methods of manufacturing the same are provided in which memory cells are manufactured with a double sided word line structure. In embodiments a first word line is located on a first side of the memory cells and a second word line is located on a second side of the memory cells opposite the first side.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Cheng-Chun Chang
  • Patent number: 11854821
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 11853890
    Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 26, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chao-Hung Wang, Yu-Hsuan Lin, Ming-Liang Wei, Dai-Ying Lee
  • Patent number: 11854941
    Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: December 26, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie Liu, Zhan Ying
  • Patent number: 11855539
    Abstract: A power converter module includes a ground terminal, an input voltage terminal configured to receive a raw input voltage, and an interconnection terminal configured to provide a regulated output voltage to a load such as a SOC or SIP system to be powered. A voltage regulator is connected to the ground terminal and the input voltage terminal. An inductor has an inductor output connected to the interconnection terminal.
    Type: Grant
    Filed: February 1, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Chih Hsu, Eric Soenen, Alan Roth