Patents by Inventor Ying Cheng

Ying Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240147690
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.
    Type: Application
    Filed: November 1, 2022
    Publication date: May 2, 2024
    Inventor: YING-CHENG CHUANG
  • Publication number: 20240147691
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 2, 2024
    Inventor: YING-CHENG CHUANG
  • Publication number: 20240145878
    Abstract: An electrode structure of rechargeable battery includes a battery tab stack, an electrode lead, a welding protective layer and a welding seam. The battery tab stack is formed by extension of a plurality of electrode sheets. The electrode lead is joined to one side of the battery tab stack. The welding protective layer is joined to another side of the battery tab stack opposite to the electrode lead. The welding seam extends from the welding protective layer to the electrode lead through the battery tab stack.
    Type: Application
    Filed: November 29, 2022
    Publication date: May 2, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kun-Tso CHEN, Tsung-Ying TSAI, Tsai-Chun LEE, Chih-Wei CHIEN, Hui-Ta CHENG
  • Patent number: 11972981
    Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Ying-Keung Leung
  • Patent number: 11969915
    Abstract: The present application disclosures a double production line and a rapid prefabrication process of a segmental beam. The double production line including two production machine and a track system provided on the construction ground; the production machine includes a fixed end mold, two side molds, a bottom mold trolley, a middle internal mold trolley and two side internal mold trolley; two side molds are positioned on two sides of the fixed end mold respectively, the fixed end mold and two side molds together define a pouring position with an end opening, two openings of the pouring position are arranged facing each other; the track system includes a transverse track and a longitudinal track communicated with each other, two pouring positions are both positioned in the extension path of the transverse track, and the longitudinal track is positioned between two pouring positions.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 30, 2024
    Assignees: CHINA RAILWAY GUANGZHOU ENGINEERING GROUP CO., LTD., China Railway Guangzhou Engineering Group Real Estate Co., Ltd.
    Inventors: Xiao Zhou, Xiaofeng Deng, Yongguang Chen, Zhouyu Xie, Gaofei Wei, Jiawei Yang, Ping Zhang, Beibei Cheng, Wenqiang Zheng, Ying Wang, Yuan Xu
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Publication number: 20240124615
    Abstract: Provided are a bispecific antibody and use thereof. The recombinant antibody includes: a CDR Sequence selected from at least one of CD3 antibody variable region CDR sequences: SEQ ID NO: 1 to SEQ ID NO: 6, and B7H6 antibody variable region CDR sequences: SEQ ID NO: 7 to SEQ ID NO: 12; or an amino acid sequence having at least 95% identity thereto. The recombinant antibodies prepared according to the present application can simultaneously target CD3 and B7H6 antigens, and they have a. significantly prolonged half-life, exhibiting a stronger tumor-inhibiting ability than single-target antibodies.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 18, 2024
    Inventors: Zhigang TIAN, Ying CHENG, Weihua XIAO, Guoshuai CAO, Haoyu SUN, Rui SUN
  • Publication number: 20240128211
    Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
  • Patent number: 11961892
    Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
  • Publication number: 20240116724
    Abstract: A container feeding device includes a casing and first and second latch members. The casing defines a lower retaining space for receiving a plurality of containers that are stacked on one another. The first latch member is operable to enter the lower retaining space for supporting a bottommost container, or leave the lower retaining space to release the bottommost container. The second latch member enters the lower retaining space to support a second bottommost container when the bottommost container is released by the first latch member.
    Type: Application
    Filed: July 27, 2023
    Publication date: April 11, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Arya Anil
  • Publication number: 20240116148
    Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.
    Type: Application
    Filed: August 28, 2023
    Publication date: April 11, 2024
    Applicant: Jabil Inc.
    Inventors: Harpuneet Singh, Lei Hu, Ying-Chieh Huang, Wei-Hsiu Hsieh, Xiao-Ting Zheng, Chien-Cheng Chu, Tike Hoong Phua, Li Yun Chee
  • Publication number: 20240115410
    Abstract: An assistive device structure for positioning and pressure relief is provided, including a first elastic layer and a second elastic layer, which are attached by using a high-frequency encapsulation process, sealing, bagging, thermoforming, or an integrally molding process. Each of the first and second elastic layers has a bottom surface and an arc surface disposed opposite to each other. The arc surface includes two protrusions and a recess formed there in between. The two protrusions have different heights. A hollow area is disposed in the recess of the first and second elastic layers. Based on such structure, the bottom surfaces of the first and second elastic layers are attached to form the proposed assistive device structure for a user to lean against and providing multiple positioning effects and pressure relief. More than four axial directions of supporting forces are generated to effectively enhance muscle relaxation and stress relief.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Inventors: SY-WEN HORNG, LONG-YING CHENG, CHI-WEI HUNG, HSIANG-JUNG HUNG, LI-CHE HUNG
  • Publication number: 20240116673
    Abstract: A transport mechanism of a server rack including a carrier plate, a server rack disposed and fixed onto a top surface of the carrier plate, and multiple supporting assemblies respectively stacked onto a bottom surface of the carrier plate is provided. Each of the supporting assemblies has at least one cushion member. The cushion member has at least one hollow portion, and an opening of the hollow portion is exposed to an environment. The stiffness of the cushion member is smaller than the stiffness of the carrier plate. A pallet structure is also provided.
    Type: Application
    Filed: November 16, 2022
    Publication date: April 11, 2024
    Applicant: Wiwynn Corporation
    Inventors: Hao-Ting Cheng, Jheng-Ying Jiang, Pei-Pei Lee
  • Patent number: 11955554
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Patent number: 11957064
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Patent number: 11955459
    Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hang Liao, Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 11951242
    Abstract: A method for performing a peritoneal dialysis therapy includes performing a plurality of peritoneal dialysis cycles for a patient and tracking an amount of dialysis fluid provided by at least one dialysis fluid pump during the plurality of peritoneal dialysis cycles. The method also includes determining an amount of ultrafiltrate (“UF”) removed from the patient based on the amount of dialysis fluid provided by the at least one dialysis fluid pump. The method further includes updating a UF trend using previous amounts of UF removed from the patient and the amount of UF removed from the patient during the most recent dialysis treatment and generating an alert if the UF trend changes by more than a preset percentage.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: April 9, 2024
    Assignees: Baxter International Inc.
    Inventors: Robert W. Childers, Ying-Cheng Lo, Peter A. Hopping
  • Publication number: 20240112701
    Abstract: Disclosed in the embodiments of the present disclosure are a method and apparatus for multimedia resource editing scene, and a device and a storage medium. The method comprises: detecting whether a current time matches a specified time; in response to determining that the current time matches the specified time, presenting prompt information of a target editing template; where the target editing template is associated with a first multimedia resource; content of the first multimedia resource belongs to a content category associated with the specified time; the target editing template instructs to edit a to-be-edited multimedia material into a second multimedia resource in a target editing way; the target editing way is an editing way used by the first multimedia resource; and the prompt information is presentation information of the first multimedia resource.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Inventors: Ying Yan, Yingzhi Zhou, Ran Cui, Yize Cheng
  • Patent number: D1024051
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Jung Huang, Hong-Kuan Li, I-Lun Li, Ling-Mei Kuo, Kuan-Ju Chen, Fang-Ying Huang, Kai-Hung Huang, Szu-Wei Yang, Kai-Teng Cheng
  • Patent number: D1024054
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: I-Lun Li, Kai-Teng Cheng, Szu-Wei Yang, Fang-Ying Huang