Abstract: Disclosed is an atomizing device, including: a housing, in which a first installation space and a host compartment are formed, the first installation space being spaced apart from the host compartment; an oil storage structure disposed in the first installation space and containing an oil storage chamber for storing oil; an atomizing tube disposed in the oil storage structure, in which an oil inlet is disposed at an air inlet end of the atomizing tube; an atomizing core disposed in the atomizing tube and spaced from the air inlet end of the atomizing tube in a longitudinal direction of the oil storage structure; and an oil guide member disposed between the atomizing tube and the atomizing core, in which the oil guide member is connected with the atomizing core, and is in communication with the oil storage chamber through the oil inlet.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: A road traffic control system includes a mobile terminal, a fixed terminal, a traffic sign, a control module, and a prompt unit. The mobile terminal includes a mobile terminal communication module for transmitting mobile terminal parameter data. The fixed terminal includes a fixed terminal communication module that is in communication connection with the mobile terminal communication module and is configured to receive the mobile terminal parameter data. The traffic sign includes a sign communication module configured to be in communication connection with the fixed terminal communication module. The control module is connected to the sign communication module. The prompt unit is connected to the control module and configured to provide a traffic instruction according to the mobile terminal parameter data.

Abstract: An electronic atomization device includes: an outer shell; and an inner shell provided in the outer shell. The inner shell includes a liquid storage cup and a battery compartment arranged side by side and independent of each other. A battery and a light strip are provided in the battery compartment. The battery is configured to supply power to the light strip. At least part of the outer shell and at least part of the battery compartment are made of a light-transmitting material.

Abstract: A method of forming a semiconductor structure includes the following operations. A trench is formed in a substrate. A dielectric layer is formed to cover an inner surface of the trench. A bottom conductive layer is deposited on the dielectric layer and in the trench at a first temperature of 350° C. to 450° C. An annealing process is performed on the bottom conductive layer at a second temperature greater than or equal to 470° C. A portion of the bottom conductive layer is removed to form a recess on the bottom conductive layer and in the trench. A top conductive layer is formed in the recess.

Abstract: Embodiments of this disclosure provide a method of manufacturing a semiconductor structure, and the method includes the following steps. A substrate with a first barrier layer in an array area and a second barrier layer in the peripheral area is provided. The substrate is etched toward to form recesses in the peripheral area to make a bottom surface of each of the recesses lower than a bottom surface of the second barrier layer. Gate structures are formed in the recesses, respectively. Moreover, a semiconductor structure is also disclosed this disclosure.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a substrate having an array area and a periphery area; forming an etch stop layer on a top surface of the substrate in the array area and the periphery area; forming a patterned mask layer on a top surface of the etch stop layer in the array area and the periphery area, in which the patterned mask layer has a plurality of hollowed portions; forming a plurality of trenches on the top surface of the etch stop layer in the array area and the periphery area through the hollowed portions of the patterned mask layer, in which the trenches run through the etch stop layer and are recessed from the top surface of the substrate; removing the patterned mask layer; and depositing an oxide layer to fill the trenches.

Abstract: A semiconductor memory device manufacturing method includes: sequentially forming a lower oxide layer, a word line metal layer and an upper oxide layer over at least a portion of a memory cell; forming a through hole passing through the upper oxide layer, the word line metal layer and the lower oxide layer to expose the portion of the memory cell; forming a sacrificial pillar into the through hole; removing the upper oxide layer to expose a top portion of the sacrificial pillar; sequentially forming a first oxide spacer sidewall, a nitride spacer sidewall and a second oxide spacer sidewall on a sidewall of the top portion of the sacrificial pillar; removing the nitride spacer sidewall to form a void gap; etching the word line metal layer through the void gap to form separate word lines.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates respectively including a recessed gate dielectric layer inwardly positioned in the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley, a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer positioned on the recessed gate top conductive layer; and a peripheral gate structure positioned on the second peripheral region. An element density of the first peripheral region is greater than an element density of the second peripheral region.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including a first peripheral region and a second peripheral region; a plurality of recessed gates respectively including a recessed gate dielectric layer inwardly positioned in the first peripheral region and including a U-shaped cross-sectional profile, a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley, a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer, and a recessed gate capping layer positioned on the recessed gate top conductive layer; and a peripheral gate structure positioned on the second peripheral region. An element density of the first peripheral region is greater than an element density of the second peripheral region.

Abstract: Dialysis is enhanced by using nanoclay sorbents to better absorb body wastes in a flow-through system. The nanoclay sorbents, using montmorillonite, bentonite, and other clays, absorb significantly more ammonium, phosphate, and creatinine, and the like, than conventional sorbents. The montmorillonite, the bentonite, and the other clays may be used in wearable systems, in which a dialysis fluid is circulated through a filter with the nanoclay sorbents. Waste products are absorbed by the montmorillonite, the bentonite, and the other clays and the dialysis fluid is recycled to a patient's peritoneum. Using an ion-exchange capability of the montmorillonite, the bentonite, and the other clays, waste ions in the dialysis fluid are replaced with desirable ions, such as calcium, magnesium, and bicarbonate. The nanoclay sorbents are also useful for refreshing a dialysis fluid used in hemodialysis and thus reducing a quantity of the dialysis fluid needed for the hemodialysis.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a recessed gate dielectric layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile; a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley; a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer; and a recessed gate capping layer positioned on the recessed gate top conductive layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a recessed gate dielectric layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile; a recessed gate bottom conductive layer positioned on the recessed gate dielectric layer and including a valley-shaped cross-sectional profile, resulting in a first valley; a recessed gate top conductive layer conformally positioned on the first valley of the recessed gate bottom conductive layer; and a recessed gate capping layer positioned on the recessed gate top conductive layer.

Abstract: A receiver for wired communication, includes a DC (direct current) level shift circuit and an analog-to-digital converter circuit. The DC level shift circuit is configured to receive a first signal and generate a second signal, in which the DC level shift circuit comprises a capacitor, and the DC level shift circuit is further configured to transmit a first common-mode voltage in a first voltage domain to a first terminal of the capacitor and transmit a second common-mode voltage in a second voltage domain to a second terminal of the capacitor before the first signal is received, and when the DC level shift circuit receives the first signal, the DC level shift circuit stops transmitting the first common-mode voltage and the second common-mode voltage to the capacitor. The analog-to-digital converter circuit is configured to generate a digital signal according to the second signal.

Abstract: Systems and methods for extracting 3D shapes from unstructured and unannotated datasets are described. Embodiments are configured to obtain a first image and a second image, where the first image depicts an object and the second image includes a corresponding object of a same object category as the object. Embodiments are further configured to generate, using an image encoder, image features for portions of the first image and for portions of the second image; identify a keypoint correspondence between a first keypoint in the first image and a second keypoint in the second image by clustering the image features corresponding to the portions of the first image and the portions of the second image; and generate, using an occupancy network, a 3D model of the object based on the keypoint correspondence.

Abstract: A semiconductor device includes a substrate, a plurality of gate structures, and a fuse component. The substrate has an active region and a peripheral region surrounding the active region. The gate structures are disposed in the active region of the substrate. The fuse component is disposed at the peripheral region of the substrate. The fuse component has a poly silicon portion having a bottom tip pointing to the substrate, a dielectric film between the substrate and the poly silicon portion, and a conductive portion on the poly silicon portion. A method of forming a semiconductor device is also disclosed.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure. The method includes: forming a conformal layer over a first patterned layer over a substrate; forming a second layer over the conformal layer and between portions of the first patterned layer; performing a first etching to form a second patterned layer and a patterned conformal layer; performing a second etching to remove a portion of the first patterned layer to form a first inclined member of the first patterned layer tapered away from the substrate and lining a vertical portion of the patterned conformal layer, and to remove a portion of the second patterned layer to form a second inclined member of the second patterned layer tapered away from the substrate and lining the vertical portion of the patterned conformal layer; and performing a third etching to remove the vertical portions of the patterned conformal layer.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a valley inwardly positioned on a top surface of the substrate; a programmable insulating layer conformally positioned on the valley and including a V-shaped cross-sectional profile; and a top electrode positioned on the programmable insulating layer. The programmable insulating layer is configured to be blown out under a programming voltage.