Patents by Inventor Ying Cheng
Ying Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12072359Abstract: A power distribution terminal provided with a display module, a wireless power distribution display system and a wireless power distribution display method are disclosed. The wireless power distribution display system includes a local gateway, and at least two power distribution terminals which are communicated with the local gateway in a short-distance wireless communication mode and send their terminal identification data to the local gateway; at least one of the at least two power distribution terminals is provided with a display module; the local gateway outputs the terminal identification data in a short-distance wireless communication mode; and the at least one power distribution terminal provided with a display module receives the terminal identification data of other distribution terminals from the local gateway in a short-distance wireless communication mode, and displays the terminal identification data.Type: GrantFiled: November 18, 2020Date of Patent: August 27, 2024Assignee: Schneider Electric Industries SASInventors: Ying Cheng, Chenglong Sun, Jiamin Chen, Xiaolong Zhu, Yun Fang, Simon Tian
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Publication number: 20240268124Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.Type: ApplicationFiled: April 16, 2024Publication date: August 8, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Publication number: 20240252729Abstract: A renal failure therapy system for performing a peritoneal dialysis therapy is disclosed. The renal failure therapy system performs a plurality of peritoneal dialysis cycles for a patient and tracks an amount of dialysis fluid provided by a dialysis fluid pump during the plurality of peritoneal dialysis cycles. The renal failure therapy system also determines, as an initial drain volume, how much dialysis fluid resides in the patient's peritoneal cavity at a start of a next dialysis treatment and determines an initial drain flow for the next dialysis treatment. The renal failure therapy system generates an alert when it is determined from the initial drain flow that a low drain flow or a drain flow stoppage could occur before the initial drain volume is recovered for the start of the next dialysis treatment.Type: ApplicationFiled: April 8, 2024Publication date: August 1, 2024Inventors: Robert W. Childers, Ying-Cheng Lo, Peter A. Hopping
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Publication number: 20240260481Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: ApplicationFiled: March 1, 2024Publication date: August 1, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Tu-Ping Wang
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Patent number: 12051666Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.Type: GrantFiled: May 9, 2022Date of Patent: July 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
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Publication number: 20240233527Abstract: A road traffic control system includes a mobile terminal, a fixed terminal, a traffic sign, a control module, and a prompt unit. The mobile terminal includes a mobile terminal communication module for transmitting mobile terminal parameter data. The fixed terminal includes a fixed terminal communication module that is in communication connection with the mobile terminal communication module and is configured to receive the mobile terminal parameter data. The traffic sign includes a sign communication module configured to be in communication connection with the fixed terminal communication module. The control module is connected to the sign communication module. The prompt unit is connected to the control module and configured to provide a traffic instruction according to the mobile terminal parameter data.Type: ApplicationFiled: April 26, 2023Publication date: July 11, 2024Inventor: CHIH-YING CHENG
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Patent number: 12029044Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.Type: GrantFiled: March 28, 2023Date of Patent: July 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Patent number: 12015017Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.Type: GrantFiled: May 17, 2021Date of Patent: June 18, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
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Publication number: 20240194591Abstract: A package structure includes a thermal dissipation structure including a substrate, a first encapsulant laterally covering the substrate, a die disposed on the substrate and including a sensing region, a second encapsulant laterally covering the die, and a redistribution structure disposed on the die and the second encapsulant. An outer sidewall of the second encapsulant is laterally offset from an outer sidewall of the first encapsulant. The die is electrically coupled to the substrate through the redistribution structure, and the redistribution structure includes a hollow region overlying the sensing region of the die.Type: ApplicationFiled: February 20, 2024Publication date: June 13, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Tsung-Hsien Chiang, Yu-Chih Huang, Chia-Hung Liu, Ban-Li Wu, Ying-Cheng Tseng, Po-Chun Lin
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Publication number: 20240194926Abstract: A containment apparatus for battery tray rack includes a pressing module, a securing module, and a controller. In response to that the containment apparatus is to form the containment on the battery tray rack, the controller controls the pressing module to apply a compressive force, so that the battery tray rack withstands a clamping pressure, and the controller controls the securing module to lock the battery tray rack to maintain the clamping pressure. In response to that the containment apparatus is to release the containment from the battery tray rack, the controller controls the pressing module to apply the compressive force, and the controller controls the securing module to unlock the battery tray rack, and then the controller controls the pressing module to cancel the compressive force.Type: ApplicationFiled: November 21, 2023Publication date: June 13, 2024Applicant: CHROMA ATE INC.Inventors: Ying-Cheng Chen, Wen-Chuan Chang, Ying-Chi Chen, Chuan-Tse Lin
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Patent number: 12009949Abstract: A signal receiver includes a first transistor, a second transistor, a load circuit, an amplifying circuit and a load circuit. The first transistor has a first end receiving a power voltage, and a control end receive a first input signal. The second transistor has a first end receiving the power voltage, and a control end receiving a second input signal, wherein the first input signal and the second input signal are differential signals and transit between a first voltage and a reference ground voltage, the first voltage is larger than the power voltage. The load circuit is coupled to the first transistor and the second transistor. The amplifying circuit generates an output signal according a first signal on the second end of the first transistor and a second signal on the second end of the second transistor.Type: GrantFiled: October 14, 2021Date of Patent: June 11, 2024Assignee: Novatek Microelectronics Corp.Inventors: Hao-Che Hsu, Chin-Tung Chan, Ying-Cheng Lin, Ren-Hong Luo
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Publication number: 20240186990Abstract: A latch includes at least one first standard cell logic gate and at least one second standard cell logic gate. The first standard cell logic gate includes a first input terminal, a second input terminal, a third input terminal, and a first output terminal. The second standard cell logic gate includes a fourth input terminal, a fifth input terminal, a sixth input terminal, and a second output terminal. The first input terminal and the second input terminal receive a first input signal. The third input terminal receives a first output signal. The first output terminal outputs a second output signal. The fourth input terminal receives the second output signal. The fifth input terminal and the sixth input terminal receive a second input signal. The second output terminal outputs the first output signal.Type: ApplicationFiled: June 9, 2023Publication date: June 6, 2024Inventors: Yun-Tse CHEN, Ying-Cheng WU, Chia-Wei YU
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Patent number: 11974966Abstract: A medical product includes a bladder, a filtration device, and a sterile product concentrate. The bladder has a perimeter seal and defining a sterile chamber. The filtration device includes a stem and a filter membrane disposed in line with the stem. The stem extends through the perimeter seal and has an inlet end accessible from outside of the perimeter seal and an outlet end in fluid communication with the sterile chamber. The filter membrane can have a nominal pore size in a range of approximately 0.1 ?m to approximately 0.5 ?m, wherein the filter membrane is shaped as a hollow fiber with a wall and pores residing in the wall of the fiber. The sterile product concentrate is disposed in the sterile chamber and adapted to be reconstituted by the introduction of a pharmaceutical fluid into the chamber through the filtration device.Type: GrantFiled: July 12, 2018Date of Patent: May 7, 2024Assignees: BAXTER INTERNATIONAL INC., BAXTER HEALTHCARE SAInventors: David Filiberto Schuck, Karl Hans Cazzini, Yuanpang Samuel Ding, Ying-Cheng Lo, Grant Anthony Bomgaars, Thomas Edward Dudar, Mark Edward Pasmore, Bernd Krause, Michael Joseph Sadowski, Anastasios Hristakos, Joseph Vincent Ranalletta
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Publication number: 20240147691Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.Type: ApplicationFiled: September 12, 2023Publication date: May 2, 2024Inventor: YING-CHENG CHUANG
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Publication number: 20240147690Abstract: A method of manufacturing a semiconductor device is provided. The method includes: providing a substrate; forming a metallization layer on the substrate; forming a first sacrificial layer and a second sacrificial layer; forming a first mask layer and a second mask layer, wherein the first mask layer covers the first sacrificial layer, the second mask layer covers the second sacrificial layer; forming a first width controlling element on a lateral surface of the first mask layer and a second width controlling element on a lateral surface of the second mask layer; removing the first mask layer and the second mask layer; and patterning the metallization layer to form a first word line between the first sacrificial layer and the second sacrificial layer, wherein a dimension of the first word line depends on a dimension of the first width controlling element.Type: ApplicationFiled: November 1, 2022Publication date: May 2, 2024Inventor: YING-CHENG CHUANG
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Publication number: 20240124615Abstract: Provided are a bispecific antibody and use thereof. The recombinant antibody includes: a CDR Sequence selected from at least one of CD3 antibody variable region CDR sequences: SEQ ID NO: 1 to SEQ ID NO: 6, and B7H6 antibody variable region CDR sequences: SEQ ID NO: 7 to SEQ ID NO: 12; or an amino acid sequence having at least 95% identity thereto. The recombinant antibodies prepared according to the present application can simultaneously target CD3 and B7H6 antigens, and they have a. significantly prolonged half-life, exhibiting a stronger tumor-inhibiting ability than single-target antibodies.Type: ApplicationFiled: December 20, 2023Publication date: April 18, 2024Inventors: Zhigang TIAN, Ying CHENG, Weihua XIAO, Guoshuai CAO, Haoyu SUN, Rui SUN
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Publication number: 20240115410Abstract: An assistive device structure for positioning and pressure relief is provided, including a first elastic layer and a second elastic layer, which are attached by using a high-frequency encapsulation process, sealing, bagging, thermoforming, or an integrally molding process. Each of the first and second elastic layers has a bottom surface and an arc surface disposed opposite to each other. The arc surface includes two protrusions and a recess formed there in between. The two protrusions have different heights. A hollow area is disposed in the recess of the first and second elastic layers. Based on such structure, the bottom surfaces of the first and second elastic layers are attached to form the proposed assistive device structure for a user to lean against and providing multiple positioning effects and pressure relief. More than four axial directions of supporting forces are generated to effectively enhance muscle relaxation and stress relief.Type: ApplicationFiled: December 18, 2023Publication date: April 11, 2024Inventors: SY-WEN HORNG, LONG-YING CHENG, CHI-WEI HUNG, HSIANG-JUNG HUNG, LI-CHE HUNG
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Patent number: 11957064Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: October 18, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11951242Abstract: A method for performing a peritoneal dialysis therapy includes performing a plurality of peritoneal dialysis cycles for a patient and tracking an amount of dialysis fluid provided by at least one dialysis fluid pump during the plurality of peritoneal dialysis cycles. The method also includes determining an amount of ultrafiltrate (“UF”) removed from the patient based on the amount of dialysis fluid provided by the at least one dialysis fluid pump. The method further includes updating a UF trend using previous amounts of UF removed from the patient and the amount of UF removed from the patient during the most recent dialysis treatment and generating an alert if the UF trend changes by more than a preset percentage.Type: GrantFiled: March 21, 2022Date of Patent: April 9, 2024Assignees: Baxter International Inc.Inventors: Robert W. Childers, Ying-Cheng Lo, Peter A. Hopping
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Publication number: 20240097216Abstract: The present invention discloses a detection device and a probe module thereof, wherein an electrical connection path between a battery detection frame and a battery under test is provided via the probe module. The probe module includes a base, a first polarity plate, a second polarity plate, a first upper connection group, a second upper connection group, a first lower connection member and a second lower connection member. Via the first polarity plate, the first upper connection group is correspondingly coupled to the battery detection frame, and the first lower connection member is correspondingly coupled to the battery under test. Via the second polarity plate, the second upper connection group is correspondingly coupled to the battery detection frame, and the second lower connection member is correspondingly coupled to the battery under test. Thus, it is not necessary to process a cable having been fixed on the battery detection frame when the probe module is replaced.Type: ApplicationFiled: June 8, 2023Publication date: March 21, 2024Inventors: CHUAN-TSE LIN, CHEN-CHOU WEN, SHIH-CHIN TAN, WEN-CHUAN CHANG, YING-CHENG CHEN