Abstract: A manufacturing method of a semiconductor package includes the following steps. A semiconductor die set is placed adjacent to a lower conductive via. The semiconductor die set and the lower conductive via are at least laterally encapsulated with a lower encapsulating material to form a lower encapsulated semiconductor device. A lower redistribution structure is formed over the lower encapsulated semiconductor device. A sensor die is placed adjacent to an upper conductive via, wherein the sensor die has a pad and a sensing region. The sensor die and the upper conductive via are encapsulated with an upper encapsulating material to form an upper encapsulated semiconductor device. An upper redistribution structure is formed over the upper encapsulated semiconductor device, wherein the upper redistribution structure is connected to the pad and reveals the sensing region of the sensor die.

Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.

Abstract: A photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Abstract: A micro-electromechanical system (MEMS) device includes a movable comb structure located in a cavity within an enclosure, and a stationary structure affixed to the enclosure. The movable comb structure includes a comb shaft portion and movable comb fingers laterally protruding from the comb shaft portion. The movable comb structure includes a metallic material portion. The movable structure and the stationary structure are configured to generate an electrical output signal based on lateral movement of the movable structure relative to the stationary structure.

Abstract: A semiconductor package includes a lower encapsulated semiconductor device, a lower redistribution structure, an upper encapsulated semiconductor device, and an upper redistribution structure. The lower redistribution structure is disposed over and electrically connected to the lower encapsulated semiconductor device. The upper encapsulated semiconductor device is disposed over the lower encapsulated semiconductor device and includes a sensor die having a pad and a sensing region, an upper encapsulating material at least laterally encapsulating the sensor die, and an upper conductive via extending through the upper encapsulating material and connected to the lower redistribution structure. The upper redistribution structure is disposed over the upper encapsulated semiconductor device. The upper redistribution structure covers the pad of the sensor die and has an opening located on the sensing region of the sensor die.

Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

Abstract: A photonic structure is provided. The photonic structure includes a guiding region, a sensing region, and logic region. The guiding region has a first side and a second side opposite to the first side. The sensing region is disposed on the second side of the guiding region. The logic region is disposed on a side of the sensing region opposite to the guiding region. The guiding region, the sensing region, and the logic region are stacked along a vertical direction. A method for manufacturing the photonic structure is also provided.

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.

Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.