Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract: According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first fin-shaped structure and a second fin-shaped structure on the substrate; forming a first epitaxial layer on the first fin-shaped structure and a second epitaxial layer on the second fin-shaped structure; and forming a cap layer on the first epitaxial layer and the second epitaxial layer. Preferably, a distance between the first epitaxial layer and the second epitaxial layer is between twice the thickness of the cap layer and four times the thickness of the cap layer.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A method of forming a semiconductor structure is provided. A substrate having a memory region is provided. A plurality of fin structures are provided and each fin structure stretching along a first direction. A plurality of gate structures are formed, and each gate structure stretches along a second direction. Next, a dielectric layer is formed on the gate structures. A first patterned mask layer is formed, wherein the first patterned mask layer has a plurality of first trenches stretching along the second direction. A second patterned mask layer on the first patterned mask layer, wherein the second patterned mask layer comprises a plurality of first patterns stretching along the first direction. Subsequently, the dielectric layer is patterned by using the first patterned mask layer and the second patterned mask layer as a mask to form a plurality of contact vias. The contact holes are filled with a conductive layer.

Abstract: A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of : providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. An epitaxial region is formed in a semiconductor substrate. A dielectric layer is formed on the epitaxial region, and a contact hole is formed in the dielectric layer. The contact hole exposes a part of the epitaxial region, and an oxide-containing layer is formed on the epitaxial region exposed by the contact hole. A contact structure is formed in the contact hole and on the oxide-containing layer. The oxide-containing layer is located between the contact structure and the epitaxial region. A semiconductor structure includes the semiconductor substrate, at least one epitaxial region, the contact structure, the oxide-containing layer, and a silicide layer. The contact structure is disposed on the epitaxial region. The oxide-containing layer is disposed between the epitaxial region and the contact structure. The silicide layer is disposed between the oxide-containing layer and the contact structure.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A method for manufacturing semiconductor devices having metal gate includes follow steps. A substrate including a plurality of isolation structures is provided. A first nFET device and a second nFET device are formed on the substrate. The first nFET device includes a first gate trench and the second nFET includes a second gate trench. A third bottom barrier layer is formed in the first gate trench and a third p-work function metal layer is formed in the second gate trench, simultaneously. The third bottom barrier layer and the third p-work function metal layer include a same material. An n-work function metal layer is formed in the first gate trench and the second gate trench. The n-work function metal layer in the first gate trench directly contacts the third bottom barrier layer, and the n-work function metal layer in the second gate trench directly contacts the third p-work function metal layer.

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor having active regions; depositing a dielectric layer on the semiconductor; forming a patterned etch mask on the dielectric layer; depositing a further dielectric layer on the dielectric layer and the patterned etch mask; planarizing the further dielectric layer until the patterned etch mask is exposed; and forming a further patterned etch mask having an opening on the further dielectric layer so that portions of the patterned etch mask are exposed from the opening.

Abstract: A gate structure is first formed on a substrate and an interlayer dielectric (ILD) layer is formed around the gate structure, a dielectric layer is formed on the ILD layer and the gate structure, an opening is formed in the dielectric layer and the ILD layer, and an organic dielectric layer (ODL) is formed on the dielectric layer and in the opening. After removing part of the ODL, part of the dielectric layer to extend the opening, and then the remaining ODL, a contact plug is formed in the opening.

Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.

Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.