Abstract: A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.

Abstract: A method of fabricating a FCBGA (Flip-Chip Ball-Grid-Array) package without causing mold flash is proposed, which is characterized by the forming of a dummy pad over the back surface of the substrate to allow the portion of the solder mask formed over a vent hole in the substrate to be substantially raised to an elevated flat surface where a groove is then formed to surround the exit of the vent hole. During a molding process, when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the groove in the elevated flat surface over the dummy pad, thereby preventing it from flashing to nearby solder-ball pads.

Abstract: An advanced flip-chip packaging technology is proposed, which is characterized in the forming of a metal dam over the substrate to serve three different utilization purposes. First, the metal dam can help provide a specific fillet width to the underfilled material under the flip chip so as to allow the joint between the flip chip and the substrate to have increased robustness against thermal stress. Second, the metal dam can serve as a mechanical reinforcement to the substrate to prevent package warpage. Third, the metal dam can additionally serve as a heat-dissipation structure to help the heat dissipation from the flip chip. These benefits allow the finished package product to be highly assured in quality and reliability.

Abstract: A semiconductor package structure for Flip Chip package includes at least an insulative core layer and a plurality of patterned circuit layers alternately stacking up each other. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of bump pads, and each of the bump pads has an etching hole. The solder mask layer covers the surface of the patterned circuit layer and a portion of the surface of the outer edge of the bump pads, and exposes the etching holes. The solder mask layer may also expose the whole surface of the bump pads.

Abstract: A flip-chip underfill method is proposed for the purpose of underfilling a gap formed beneath a semiconductor chip mounted in a flip-chip manner over an underlying surface. The flip-chip underfill method comprises the following procedural steps of: preparing a dispensing needle having an outlet; then, moving the dispensing needle in such a manner as to position the outlet thereof at a corner point between the upper surface and the sidewall of the semiconductor chip; and finally injecting resin at the targeted corner point, which allows the injected resin from the outlet of the dispensing needle to flow down along the sidewall of the semiconductor chip to the edge of the lower surface of the semiconductor chip and subsequently fill into the gap through capillary action.

Abstract: A flip-chip packaging process is proposed, which can help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads without being made open-circuited by the electrically-insulative material being used for flip chip underfill. The proposed flip-chip packaging process is of the type utilizing a no-flow underfill technique to prevent short-circuiting between neighboring solder bumps, and is characterized in the fabrication of electrically-conductive sharp-pointed studs over substrate-side bond pads to prevent open-circuiting between chip-side solder bumps and substrate-side bond pads.

Abstract: An advanced flip-chip packaging technology is proposed, which is characterized in the forming of a metal dam over the substrate to serve three different utilization purposes. First, the metal dam can help provide a specific fillet width to the underfilled material under the flip chip so as to allow the joint between the flip chip and the substrate to have increased robustness against thermal stress. Second, the metal dam can serve as a mechanical reinforcement to the substrate to prevent package warpage. Third, the metal dam can additionally serve as a heat-dissipation structure to help the heat dissipation from the flip chip. These benefits allow the finished package product to be highly assured in quality and reliability.

Abstract: A method of fabricating a FCBGA (Flip-Chip Ball-Grid-Array) package without causing mold flash is proposed, which is characterized by the forming of a dummy pad over the back surface of the substrate to allow the portion of the solder mask formed over a vent hole in the substrate to be substantially raised to an elevated flat surface where a groove is then formed to surround the exit of the vent hole. Dunng molding process when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the groove in the elevated flat surface over the dummy pad, thereby preventing it from flashing to nearby solder-ball pads.

Abstract: A flip-chip bonding structure on substrate for flip-chip package application is proposed, on which solder bumps can be bonded for electrically coupling a flip chip to the substrate. The proposed flip-chip bonding structure is characterized in that its solder-bump pads can be dimensionally-invariable irrespective of a positional deviation in solder mask due to misalignment. Moreover, the proposed flip-chip bonding structure can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that neighboring solder bumps would be less likely short-circuited to each other and flip-chip underfill can be more easily implemented.

Abstract: An underfill method is proposed for performing flip-chip underfill in an integrated circuit package of the type based on a WBCOCBGA (Wire-Bonded Chip-On-Chip Ball-Grid Array) construction which includes two semiconductor chips arranged in a chip-on-chip (COC) manner, wherein the underlying chip is electrically coupled to the substrate by means of wire bonding (WB), while the overlying chip is mounted in a flip-chip manner over the underlying chip and electrically coupled to the same by means of ball grid array (BGA) technology. The proposed method is characterized in the forming of an elongated dam structure over a preserved side surface area of the underlying chip beside the bonding wires connected to the underlying chip. During the dispensing process, the dispensed resin can fill into the gap under the overlying chip through capillary action while being prevented from coming in touch with the nearby bonding wires by the dam structure.

Abstract: An advanced flip-chip packaging technology is proposed, which is characterized in the forming of a metal dam over the substrate to serve three different utilization purposes. First, the metal dam can help provide a specific fillet width to the underfilled material under the flip chip so as to allow the joint between the flip chip and the substrate to have increased robustness against thermal stress. Second, the metal dam can serve as a mechanical reinforcement to the substrate to prevent package warpage. Third, the metal dam can additionally serve as a heat-dissipation structure to help the beat dissipation from the flip chip. These benefits allow the finished package product to be highly assured in quality and reliability.

Abstract: A pattern layout structure of package substrate includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers wherein the patterned circuit layers are electrically connected each other. The feature of the pattern layout is that the patterned circuit layer includes a signal circuit region, a power/ground region, and a dummy circuit region. The signal circuit region includes a multiplicity of conductive traces, and the power/ground region includes a first grid-like pattern while the dummy circuit region includes a second grid-like pattern. The pitch of either the first or second grid patterns is equal to the pitch of the conductive traces.

Abstract: A bump structure formed having dopants therein. The bump structure includes a substrate, a plurality of bonding pads, a die and a plurality of bumps. The substrate has a first surface. The plurality of bonding pads is formed on the first surface of the substrate. The die has an active surface. Each bump at least includes a base and a plurality of dopants. The bumps are formed on the active surface of the die. The active surface of the die faces the first surface of the substrate. The substrate and the die are aligned such that each bump on the die corresponds with a bonding pad on the substrate. Dopants in the bump structure are made to contact the bonding pads on the substrate.