Abstract: To provide porous monodispersed particles obtained by preparing, as seed particles, poly(methyl methacrylate) particles or acrylic resin particles comprising 70% by mass or more of methyl methacrylate as a copolymerization component, swelling the seed particles 20 to 80 times the size of the original seed particles by mass using a swelling solution comprising an oil-soluble polymerization initiator and a monomer mixture containing 70% by mass or more of methyl methacrylate and 3 to 8% by mass of divinylbenzene, and polymerizing the monomers. The particles are porous particles with a diameter of the order of micrometers and a narrow particle-size distribution and are monodispersed. Colored monodispersed particles obtained by agglomerating a pigment in the porous monodispersed particles are monodispersed and spherical, and contain a large amount of pigment therein.

Abstract: According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image data corresponding to the determined segment mode; accumulating a value of the selected portion of the received image data; comparing the accumulated value to a threshold value; and generating an interrupt signal if the accumulated value exceeds the threshold value.

Abstract: A method of identifying an antiviral agent effective against viruses, which utilize ?1 programmed ribosomal frameshifting is provided. The method includes providing cells harboring a ?1 frame plasmid including a translation start site followed by a ?1 ribosomal frameshifting signal followed by a reporter gene which is in a ?1 frame relative to the translation start site. The method further includes contacting the cells with a test agent; and measuring the activity of the reporter gene in the presence of the test agent, wherein the reporter gene activity is dependent on ?1 ribosomal frameshifting.

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract: A method and apparatus for enabling power management of a flat-panel display is described. In one embodiment, a method involves detecting at least one display device power state and adjusting a backlight brightness in a display monitor in response to the detecting the at least one display power state. In one embodiment, a method further involves altering the brightness of a display image in order to maintain a display image quality when the backlight is adjusted.

Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each counter counting several different byte values as they occur with the first idle frame. A first subset of the possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second set of pixel byte values satisfy a threshold.

Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each counter counting several different byte values as they occur with the first idle frame. A first subset of the possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second set of pixel byte values satisfy a threshold.

Abstract: According to one embodiment of the present invention, a method of power management for a flat panel display is disclosed. The method includes: receiving image data; determining a segment mode for the received image data; selecting a portion of the received image data corresponding to the determined segment mode; accumulating a value of the selected portion of the received image data; comparing the accumulated value to a threshold value; and generating an interrupt signal if the accumulated value exceeds the threshold value.

Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each counter counting several different byte values as they occur with the first idle frame. A first subset of the possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second set of pixel byte values satisfy a threshold.

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract: An apparatus for image contrast modulation includes a memory for storing a scaling factor and a memory for storing a pixel position. A pixel determiner calculates the position of another pixel based upon the pixel position and the scaling factor. A segment determiner ascertains which segment of the segmented line contains the pixel position. A coefficient generator determines which coefficient is associated with the line segment. A method for image contrast modulation includes defining at least one multi-segmented line that approximates a higher order curve including more than one pixel in a source image, and line-fitting pixel intensity values in a scaled image according to a multi-segmented line.

Abstract: A method and apparatus for reducing video data. The apparatus is composed of a plurality of reducers. A block is received, corresponding to a plurality of color space components and having a width defined by a plurality of pixels digitally represented by bytes. The video data is first reduced by performing power of two reduction. This is followed by fine scale reduction to achieve the final reduced image.

Abstract: A method and apparatus for video motion compensation, power of two reduction and color format conversion is disclosed. The motion compensation engine performs the MPEG-2 functions of half pel compensation, inverse discrete cosine transform and merge. Dual prime, field-based and frame-based macroblocks are supported. Data reduction may be performed in the vertical direction, the horizontal direction, or both.

Abstract: Idle frames received by a graphics controller are compressed by evaluating two idle frames to create an encoding table used to replace selected pixel byte values in subsequent idle frames with codes. Possible pixel byte values are associated with a first set of counters, with each counter counting several different byte values as they occur with the first idle frame. A first subset of the possible pixel byte values is selected based on the counts in the first counters and each byte value in the first subset is associated with a second counter. The occurrences of the first subset of pixel byte values are counted in the second idle frame, and a second subset of pixel byte values is selected based on the counts in the second counters and used to create the encoding table. In one aspect, the encoding table is created when the second set of pixel byte values satisfy a threshold.

Abstract: A method and apparatus for enabling power management of a flat-panel display is described. In one embodiment, a method involves detecting at least one display device power state and adjusting a backlight brightness in a display monitor in response to said detecting said at least one display power state. In one embodiment, a method further involves altering the brightness of a display image in order to maintain a display image quality when the backlight is adjusted.

Abstract: A method and system to use a standard cell function library to automatically configure gate array cells in an integrated circuit layout is provided. A standard cell netlist at the transistor level is compiled to list the transistors required in implementing the desired functions. Based on the netlist, gate array cells are restructured so that they can be inserted in locations designed for standard cells. The restructured gate array cells, which are made up of single poly and double poly structures, are strategically placed in a layout. Using the function net connectivity patterns from the standard cell function library, the gate array cells are connected to implement desired logic functions.