Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.

Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Abstract: A display substrate includes a substrate; a first pixel defining layer on the substrate, wherein the first pixel defining layer has a first container portion therein; a planarization pattern filled in the first container portion, wherein a surface of the planarization pattern distal to the substrate is flush with a surface of the first pixel defining layer distal to the substrate; a second pixel defining layer on a side of the planarization pattern distal to the substrate, wherein a second container portion is in the second pixel defining layer and penetrates through the second pixel defining layer along a stacking direction of the first pixel defining layer and the substrate, and an orthographic projection of the second container portion on the substrate falls within an orthographic projection of the first container portion on the substrate; and an organic functional layer in the second container portion.

Abstract: A multi-spectral temperature measuring device based on adaptive emissivity model and temperature measuring method thereof are provided, which is configured to measure the temperature of the surface of an object under a high temperature background. The present invention relates to the technical field of radiation temperature measurement. The present invention provides a multi-spectral temperature measurement device based on an adaptive emissivity model, includes a pyrometer, a radiation detector, a constant temperature furnace, a cooling cavity, a cold air inlet pipe, a cold air outlet tube, and a thermocouple and thermocouple acquisition card. In order to more accurately measure the surface temperature of the object in a high-temperature environment, a BP network is provided to adaptively find the emissivity model, and through pre-training the network, the network has a high degree of recognition, and then classifies the spectral curve to accurately output the corresponding emissivity model.

Abstract: A display substrate including a base substrate and a pixel defining layer is provided. The pixel defining layer includes a first defining layer and a second defining layer, which define a plurality of lower openings and a plurality of upper openings corresponding to the plurality of lower openings, respectively. An orthographic projection of a bottom surface of each upper opening on the base substrate covers that of a corresponding lower opening on the base substrate, orthographic projections of bottom surfaces of the plurality of upper openings on the base substrate have an equal area. The plurality of lower openings include a first lower opening, a second lower opening and a third lower opening, which form a first cavity, a second cavity and a third cavity respectively together with a corresponding upper opening.

Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes an insulating pattern whose surface layer is composed of a hydrophobic fluorine-containing material, so the organic ink used to prepare a light emitting layer does not overflow outside a pixel area. The method for preparing the display substrate includes: forming a rheological insulating material layer on the base substrate; curing the rheological insulating material layer, and patterning the cured insulating material layer to obtain an insulating pattern; heating the insulating pattern, to gather the hydrophobic insulating structure on a surface of the insulating pattern away from the base substrate; heating the gathered hydrophobic insulating structure to melt it, and then cooling the molten hydrophobic insulating structure to form a metal pattern on the surface of the insulating pattern.

Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.

Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: The disclosure discloses an organic light-emitting display panel, a method for fabricating the same, and a display device, and the method for fabricating an organic light-emitting display panel includes: providing a substrate; and forming light-emitting layers sequentially in opening regions of sub-pixels in different colors, wherein at least one of sub-pixels other than a sub-pixel with a largest area is a first sub-pixel, and sub-pixels other than the first sub-pixel are second sub-pixels; and forming a light-emitting layer for the first sub-pixel includes: jetting a solvent for dissolving a light-emitting material in at least one of the second sub-pixels in which no light-emitting layer is formed, and jetting ink including the solvent, and a light-emitting material corresponding to the first sub-pixel in the first sub-pixel.

Abstract: The present disclosure provides an array substrate, including: a base substrate; a planarization layer formed on the base substrate; a plurality of pixel electrodes formed on the planarization layer; and a pixel definition layer including a first pixel definition layer and a second pixel definition layer, the first pixel definition layer covering a periphery of each pixel electrode and exposing a central area of each pixel electrode, the second pixel definition layer being formed on the planarization layer between adjacent pixel electrodes and having a plurality of openings defining each sub-pixel unit; a bottom of a dam portion of the second pixel definition layer and a bottom of a dam portion of the first pixel definition layer adjacent thereto are separated by a predetermined distance, and a thickness of the second pixel definition layer is greater than a thickness of the first pixel definition layer.

Abstract: A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

Abstract: When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.

Abstract: A display substrate and a fabrication method thereof, and a display panel are disclosed. The display substrate includes: a base substrate; a pixel defining layer, on the base substrate and configured to define a plurality of sub-pixel regions, each sub-pixel region including a first electrode layer and a second electrode layer; an auxiliary electrode layer, on at least a portion of the pixel defining layer, the auxiliary electrode layer having a hydrophobic surface, and the hydrophobic surface being configured to be in contact with and electrically connected with the second electrode layer.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Abstract: When programming a memory device which includes a plurality of memory cells coupled to a plurality of word lines and a plurality of bit lines, coarse programming is perform on two adjacent first and second word lines among the plurality of word lines. Next, an unselected bit line among the plurality of bit lines is pre-charged during a first period after performing the coarse programming on the first word line and the second word line. Also, the channel between the unselected bit line and the second word line is turned on at the start of the first period and turned off prior to the end of the first period. Then, fine programming is performed on the first word line during a second period subsequent to the first period.

Abstract: A transparent display panel includes a base, a first pixel defining structure and a first light-emitting devices. The first pixel defining structure is disposed on the base and includes a first opening that has a light transmission region and a light-emitting region. The first light-emitting device is disposed on the base and includes an opaque electrode and a light-emitting functional layer. At least part of the opaque electrode is exposed by the first opening, and an orthographic projection of the opaque electrode does not overlap with the light transmission region. The light-emitting functional layer is disposed in the first opening and defined by the first opening. The orthographic projection of the opaque electrode and an orthographic projection of the light-emitting functional layer have an overlapping region, and at least a portion of the overlapping region is within the light-emitting region.