Patents by Inventor Ying-Hao Chen
Ying-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105460Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20240096732Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.Type: ApplicationFiled: January 13, 2023Publication date: March 21, 2024Inventors: Chih-Hao CHEN, Li-Hui CHENG, Ying-Ching SHIH
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Publication number: 20240088225Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11923396Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
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Publication number: 20240071535Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.Type: ApplicationFiled: October 16, 2022Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
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Publication number: 20240071847Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Publication number: 20230402478Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: ApplicationFiled: August 9, 2023Publication date: December 14, 2023Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11810933Abstract: A method for fabricating an image sensor device is provided. The method includes forming a plurality of photosensitive pixels in a substrate; depositing a dielectric layer over the substrate; etching the dielectric layer, resulting in a first trench in the dielectric layer and laterally surrounding the photosensitive pixels; and forming a light blocking structure in the first trench, such that the light blocking structure laterally surrounds the photosensitive pixels.Type: GrantFiled: September 2, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11798969Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: GrantFiled: June 15, 2022Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11769780Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.Type: GrantFiled: July 23, 2020Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
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Publication number: 20230253284Abstract: The present disclosure describes heat dissipation structures formed in functional or non- functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.Type: ApplicationFiled: April 19, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Publication number: 20230207693Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. The semiconductor device includes an isolation structure in the semiconductor substrate. The isolation structure surrounds an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate is across the active region and extends onto the isolation structure. The semiconductor device includes a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
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Patent number: 11670562Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.Type: GrantFiled: November 30, 2020Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11600727Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.Type: GrantFiled: June 4, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
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Patent number: 11569288Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.Type: GrantFiled: April 8, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11569289Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.Type: GrantFiled: August 24, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Publication number: 20220384497Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Chien HSIEH, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
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Publication number: 20220367549Abstract: An image sensor device includes a substrate, photosensitive pixels, an interconnect structure, a dielectric layer, and a light blocking element. The photosensitive pixels are in the substrate. The interconnect structure is over a first side of the substrate. The dielectric layer is over a second side of the substrate opposite the first side of the substrate. The light blocking element has a first portion extending over a top surface of the dielectric layer and a second portion extending in the dielectric layer. The second portion of the light blocking element laterally surrounds the photosensitive pixels.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Wei-Li HU, Kuo-Cheng LEE, Ying-Hao CHEN
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Publication number: 20220310677Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11367745Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: GrantFiled: August 20, 2020Date of Patent: June 21, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen