Patents by Inventor Ying-Hao Chen

Ying-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10971370
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Publication number: 20210082784
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
  • Patent number: 10943791
    Abstract: In a pattern formation method, a photo resist pattern is formed over a target layer to be patterned. An extension material layer is formed on the photo resist pattern. The target layer is patterned by using at least the extension material layer as an etching mask.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Chang Lee, Jiann-Horng Lin, Chih-Hao Chen, Ying-Hao Wu, Wen-Yen Chen, Shih-Hua Tseng, Shu-Huei Suen
  • Publication number: 20210057517
    Abstract: The present disclosure relates to an apparatus that includes a bottom electrode and a dielectric structure. The dielectric structure includes a first dielectric layer on the bottom electrode and the first dielectric layer has a first thickness. The apparatus also includes a blocking layer on the first dielectric layer and a second dielectric layer on the blocking layer. The second dielectric layer has a second thickness that is less than the first thickness. The apparatus further includes a top electrode over the dielectric structure.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Ting CHEN, Tsung-Han Tsai, Kun-Tsang Chuang, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Chuang
  • Publication number: 20210050281
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Application
    Filed: October 19, 2020
    Publication date: February 18, 2021
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 10905020
    Abstract: An electronic device includes a first body, a second body, a hinge mechanism, two driving mechanisms, at least two lifting mechanisms, and a flexible panel. The first body is connected to the second body through the hinge mechanism. The two driving mechanisms are disposed in the first and second bodies, respectively, and the hinge mechanism is connected to the two driving mechanisms. The lifting mechanisms are respectively disposed in the first body and the second body, and each lifting mechanism is connected to the corresponding driving mechanism. The hinge mechanism is configured to drive the two driving mechanisms which respectively drive the two lifting mechanisms to ascend or descend. The flexible panel includes a first bonding portion secured to the first body, a second bonding portion secured to the second body, and a bending portion between the first and second bonding portions. The bending portion contacts the two lifting mechanisms.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: January 26, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Shiue Jan, Wei-Hao Lan, Pai-Feng Chen, Han-Tsai Liu, Ying-Hua Chiang, Jyh-Chyang Tzou
  • Publication number: 20210020671
    Abstract: A back side illumination (BSI) image sensor is provided. The BSI image sensor includes a semiconductor substrate, a first dielectric layer, a reflective element, a second dielectric layer and a color filter layer. The semiconductor substrate has a front side and a back side. The first dielectric layer is disposed on the front side of the semiconductor substrate. The reflective element is disposed on the first dielectric layer, in which the reflective element has an inner sidewall contacting the first dielectric layer, and the inner sidewall has a zigzag profile. The second dielectric layer is disposed on the first dielectric layer and the reflective element. The color filter layer is disposed on the backside of the semiconductor substrate.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
  • Patent number: 10895894
    Abstract: An electronic device includes a first body, a second body, a hinge structure, an ascending/descending mechanism, and a flexible screen. The hinge structure is located between the first body and the second body, and the first body is connected to the second body through the hinge structure. At least one of the first body and the second body has an accommodating space. The ascending/descending mechanism is disposed in the accommodating space and connected to the hinge structure. The flexible screen includes a first bonding portion fixed to the first body, a second bonding portion fixed to the second body, and a bending portion located between the first and second bonding portions. The bending portion is aligned to the hinge structure and the ascending/descending mechanism. The ascending/descending mechanism is driven by the hinge structure to ascend or descend, so that the bending portion moves out of or into the accommodating space.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 19, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Cheng-Shiue Jan, Wei-Hao Lan, Pai-Feng Chen, Han-Tsai Liu, Ying-Hua Chiang, Jyh-Chyang Tzou
  • Publication number: 20200407261
    Abstract: Glass separation systems for separating glass substrates from a continuous glass ribbon are disclosed. In one embodiment, the system may include an A-surface nosing bar positioned on a first side of a glass conveyance pathway. A long axis of the A-surface nosing bar may be substantially orthogonal to a conveyance direction of the glass conveyance pathway. The glass separation system may further comprise a B-surface nosing bar positioned on a second side of the glass conveyance pathway and opposite the A-surface nosing bar. A long axis of the B-surface nosing bar may be substantially orthogonal to the conveyance direction of the glass conveyance pathway. The A-surface nosing bar and the B-surface nosing bar may be pivotable about axes of rotation parallel to the conveyance direction of the glass conveyance pathway.
    Type: Application
    Filed: February 5, 2019
    Publication date: December 31, 2020
    Inventors: Tai Hsin Chang, Kun Chih Chen, Ying Hao Chen, Charles Robert Rumsey
  • Patent number: 10866362
    Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen, Tien-l Bao
  • Patent number: 10868178
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Patent number: 10854530
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 10825684
    Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Hao Chang, Chien-Chih Chen, Kuo-Chang Kau, Jeng-Horng Chen, Pi-Yeh Chia, Chi-Ren Chen, Ying-Chih Lin
  • Patent number: 10818583
    Abstract: Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: I-Ting Chen, Ying-Ching Shih, Po-Hao Tsai, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10811338
    Abstract: A surface treatment and an apparatus for semiconductor packaging are provided. A surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Horng Chang, Jie-Cheng Deng, Tin-Hao Kuo, Ying-Yu Chen
  • Patent number: 10784375
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • Publication number: 20200295188
    Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
  • Patent number: 10771766
    Abstract: Various examples with respect to method and apparatus for active stereo vision are described. An apparatus may include an electromagnetic (EM) wave emitter, a first sensor and a second sensor. During operation, the EM wave emitter emits EM waves toward a scene, the first sensor captures a first image of the scene in an infrared (IR) spectrum, and the second sensor captures a second image of the scene in a light spectrum. The first image and second image, when processed, may enable active stereo vision.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: September 8, 2020
    Assignee: MEDIATEK INC.
    Inventors: Han-Yang Wang, Yu-Chun Chen, Po-Hao Huang, Chao-Chung Cheng, Ying-Jui Chen, Te-Hao Chang
  • Publication number: 20200279944
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Patent number: 10755392
    Abstract: A video controller and method for performing tone-mapping of high-dynamic-range (HDR) video are provided. The video controller includes: a color-space converter, arranged to receive an input high-dynamic-range (HDR) video signal and perform a color space conversion on the input HDR video signal to obtain a first video signal having a first gamma curve; a de-gamma unit, arranged to apply a second gamma curve on the first video signal to compensate the first gamma curve to obtain a second video signal; a first histogram calculator, arranged to calculate a first histogram of a current frame of the second video signal; and a tone-mapping unit, arranged to apply a tone-mapping curve on the current frame of the second video signal according to a histogram of a previous frame of the second video signal to generate an output video signal.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 25, 2020
    Assignee: MEDIATEK INC.
    Inventors: Ying-Ru Chen, Wen-Fu Lee, Te-Hao Chang, Tai-Hsiang Huang