Patents by Inventor Ying-Hao Chen
Ying-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12224297Abstract: A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.Type: GrantFiled: January 19, 2023Date of Patent: February 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 12154933Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.Type: GrantFiled: July 29, 2022Date of Patent: November 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
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Publication number: 20240387595Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.Type: ApplicationFiled: July 31, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Chien HSIEH, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
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Patent number: 12113086Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: GrantFiled: August 9, 2023Date of Patent: October 8, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Publication number: 20240332115Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.Type: ApplicationFiled: June 11, 2024Publication date: October 3, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
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Patent number: 12046528Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.Type: GrantFiled: April 19, 2023Date of Patent: July 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11990365Abstract: A method for manufacturing a semiconductor device includes forming a metal layer in a substrate and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-filling layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first via communicating with the opening in the gap-filling layer, and an upper portion of the opening is widened to form a trench. The method includes performing a third etching step to remove the gap-filling layer in a bottom of the opening and to deepen both the trench and the opening. The method includes forming a second via communicating with the opening to expose the metal layer.Type: GrantFiled: December 2, 2021Date of Patent: May 21, 2024Assignee: WINBOND ELECTRONICS CORP.Inventors: Chang-Ju Ho, Kao-Tsair Tsai, Ying-Hao Chen
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Publication number: 20230402478Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: ApplicationFiled: August 9, 2023Publication date: December 14, 2023Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11810933Abstract: A method for fabricating an image sensor device is provided. The method includes forming a plurality of photosensitive pixels in a substrate; depositing a dielectric layer over the substrate; etching the dielectric layer, resulting in a first trench in the dielectric layer and laterally surrounding the photosensitive pixels; and forming a light blocking structure in the first trench, such that the light blocking structure laterally surrounds the photosensitive pixels.Type: GrantFiled: September 2, 2020Date of Patent: November 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11798969Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: GrantFiled: June 15, 2022Date of Patent: October 24, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11769780Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.Type: GrantFiled: July 23, 2020Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
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Publication number: 20230253284Abstract: The present disclosure describes heat dissipation structures formed in functional or non- functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.Type: ApplicationFiled: April 19, 2023Publication date: August 10, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei CHENG, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Publication number: 20230207693Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate. The semiconductor device includes an isolation structure in the semiconductor substrate. The isolation structure surrounds an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate is across the active region and extends onto the isolation structure. The semiconductor device includes a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure.Type: ApplicationFiled: March 2, 2023Publication date: June 29, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
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Patent number: 11670562Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.Type: GrantFiled: November 30, 2020Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11600727Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate. The method includes forming a gate over the semiconductor substrate. The method includes forming a support film over the isolation structure. The support film is a continuous film which continuously covers the isolation structure and the gate over the isolation structure, the support film conformally covers a first portion of a top surface and a second portion of a first sidewall of the gate, the top surface faces away from the semiconductor substrate, the support film and a topmost surface of the active region do not overlap with each other, and the topmost surface faces the gate. The method includes after forming the support film, forming lightly doped regions in the semiconductor substrate and at two opposite sides of the gate.Type: GrantFiled: June 4, 2020Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
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Patent number: 11569288Abstract: A semiconductor structure includes a sensor chip. The sensor chip includes a pixel array region, a bonding pad region, and a periphery region surrounding the pixel array region. The semiconductor structure further includes a stress-releasing trench, wherein the stress-releasing trench is in the periphery region, and the stress-releasing trench fully surrounds a perimeter of the pixel array region and the bonding pad region.Type: GrantFiled: April 8, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Patent number: 11569289Abstract: A semiconductor structure includes a substrate having a pixel array region and a first seal ring region, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The semiconductor structure further includes a first isolation feature in the first seal ring region, wherein the first isolation feature is filled with a dielectric material, and the first isolation feature is a continuous structure surrounding the pixel array region. The semiconductor structure further includes a second isolation feature between the first isolation feature and the pixel array region, wherein the second isolation feature is filled with the dielectric material.Type: GrantFiled: August 24, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Publication number: 20220384497Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.Type: ApplicationFiled: July 29, 2022Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Chien HSIEH, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
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Publication number: 20220367549Abstract: An image sensor device includes a substrate, photosensitive pixels, an interconnect structure, a dielectric layer, and a light blocking element. The photosensitive pixels are in the substrate. The interconnect structure is over a first side of the substrate. The dielectric layer is over a second side of the substrate opposite the first side of the substrate. The light blocking element has a first portion extending over a top surface of the dielectric layer and a second portion extending in the dielectric layer. The second portion of the light blocking element laterally surrounds the photosensitive pixels.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Chien HSIEH, Yun-Wei CHENG, Wei-Li HU, Kuo-Cheng LEE, Ying-Hao CHEN
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Publication number: 20220310677Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.Type: ApplicationFiled: June 15, 2022Publication date: September 29, 2022Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen