Patents by Inventor Ying-Hao Chen
Ying-Hao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200135789Abstract: A semiconductor structure includes a sensor wafer comprising a plurality of sensor chips on and within a substrate. Each of the plurality of sensor chips includes a pixel array region, a bonding pad region, and a periphery region. The periphery region is between adjacent to a scribe line, and the scribe line is between adjacent sensor chips of the plurality of sensor chips. Each of the plurality of sensor chips further includes a stress-releasing trench structure embedded in the substrate, wherein the stress-releasing trench structure is in the periphery region, and the stress-releasing trench structure fully surrounds a perimeter of the pixel array region and the bonding pad region of a corresponding sensor chip of the plurality of sensor chips.Type: ApplicationFiled: October 3, 2019Publication date: April 30, 2020Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN, Chun-Wei CHIA
-
Patent number: 10516048Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.Type: GrantFiled: November 6, 2017Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
-
Patent number: 10090392Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.Type: GrantFiled: January 17, 2014Date of Patent: October 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: I-Chih Chen, Chih-Mu Huang, Ling-Sung Wang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
-
Publication number: 20180061987Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: I-Chih CHEN, Ying-Lang WANG, Chih-Mu HUANG, Ying-Hao CHEN, Wen-Chang KUO, Jung-Chi JENG
-
Patent number: 9865731Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.Type: GrantFiled: November 15, 2013Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
-
Publication number: 20170338342Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation structure surrounds an active region of the semiconductor substrate. The method also includes forming a gate over the semiconductor substrate, and the gate is across the active region and extends onto the isolation structure. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are over the isolation structure. The method includes forming a support film over the isolation structure, and the support film is a continuous film which continuously covers the isolation structure and at least one end portion of the gate.Type: ApplicationFiled: August 7, 2017Publication date: November 23, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
-
Patent number: 9812569Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.Type: GrantFiled: March 25, 2014Date of Patent: November 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
-
Patent number: 9768221Abstract: A semiconductor device including a light sensing region disposed on a substrate is provided that includes a bond structure having one or more patterned layers underlying the pad element. The pad element may be coupled to the light sensing region and may be formed in a first metal layer disposed on the substrate. A second metal layer of the device has a first bond region, a region of the second metal layer that underlies the pad element. This first bond region of the second metal layer includes a pattern of a plurality of conductive lines interposed by dielectric. A via connects the pad element and the second metal layer.Type: GrantFiled: June 27, 2013Date of Patent: September 19, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shang-Yen Wu, I-Chih Chen, Yi-Sheng Liu, Volume Chien, Fu-Tsun Tsai, Chi-Cherng Jeng, Ying-Hao Chen
-
Patent number: 9728637Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.Type: GrantFiled: November 14, 2013Date of Patent: August 8, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
-
Patent number: 9728511Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.Type: GrantFiled: December 17, 2013Date of Patent: August 8, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsi-Jung Wu, Volume Chien, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang
-
Patent number: 9659859Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.Type: GrantFiled: July 27, 2015Date of Patent: May 23, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin
-
Publication number: 20160148967Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.Type: ApplicationFiled: February 1, 2016Publication date: May 26, 2016Inventors: Volume Chien, I-Chih Chen, Hsin-Chi Chen, Hung-Ta Huang, Ying-Hao Chen, Ying-Lang Wang
-
Patent number: 9281215Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.Type: GrantFiled: November 14, 2013Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., LTD.Inventors: Jung-Chi Jeng, I-Chih Chen, Wen-Chang Kuo, Ying-Hao Chen, Ru-Shang Hsiao, Chih-Mu Huang
-
Patent number: 9252180Abstract: A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.Type: GrantFiled: February 8, 2013Date of Patent: February 2, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Volume Chien, I-Chih Chen, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang
-
Publication number: 20150333007Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.Type: ApplicationFiled: July 27, 2015Publication date: November 19, 2015Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin
-
Patent number: 9093430Abstract: A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold.Type: GrantFiled: October 21, 2013Date of Patent: July 28, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Chih Chen, Ying-Hao Chen, Chi-Cherng Jeng, Volume Chien, Fu-Tsun Tsai, Kun-Huei Lin
-
Publication number: 20150206945Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: I-CHIH CHEN, CHIH-MU HUANG, LING-SUNG WANG, YING-HAO CHEN, WEN-CHANG KUO, JUNG-CHI JENG
-
Publication number: 20150200299Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.Type: ApplicationFiled: March 25, 2014Publication date: July 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Chih CHEN, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
-
Publication number: 20150170985Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.Type: ApplicationFiled: December 17, 2013Publication date: June 18, 2015Applicant: Taiwan Semiconductor Manufacturing CO., LTD.Inventors: Hsi-Jung Wu, Volume Chien, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang
-
Publication number: 20150137247Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-CHIH CHEN, YING-LANG WANG, CHIH-MU HUANG, YING-HAO CHEN, WEN-CHANG KUO, JUNG-CHI JENG