Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first plurality of interconnects within a first dielectric structure on a first substrate, and a second plurality of interconnects within a second dielectric structure on a second substrate. A bonding structure is arranged between the first dielectric structure and the second substrate. An inter-tier interconnect structure extends between the first plurality of interconnects and the second plurality of interconnects and through the second substrate. The inter-tier interconnect structure includes a first region having substantially vertical sidewalls extending through the second substrate and a second region surrounded by the bonding structure. The second region contacts a bottom of the first region and has tapered sidewalls.

Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Abstract: Methods, apparatus, and systems for determining whether a handover between network nodes should occur, and methods for performing handover. The disclosure relates to mechanisms to for performing mobility in an IAB network by exchanging information, such as mobility configuration information and mobility assistance information, among others.

Abstract: Various embodiments of the present disclosure are directed towards a method for nondestructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.

Abstract: A method for network handover includes acquiring status information of a current network and network preference information. It is determined whether the current network satisfies the acquired network preference information and the acquired status information. A network handover indication related to the current network is generated according to a result of the determination.

Abstract: Methods, apparatus, and systems for improving migrations in wireless systems during handover of integrated access and backhaul (IAB) nodes between central units (CU), where one or more user equipment or mobile terminals are connected to an IAB node. The disclosure relates to communicating configuration information for a gradual handover to prevent interference and packet loss.

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor’s source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor’s channel region and extends downward into a recess that exposes the lower transistor’s source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor’s source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure.

Abstract: Disclosed are a touch panel, a touch device, and a touch display device. The touch panel has a touch area, and the touch panel includes at least two first type electrode layers which are stacked, the first type electrode layer having a first type touch sensing area, and respective first type touch sensing areas of the at least two first type electrode layers being spliced and filled in the touch area. In the embodiments of the present disclosure, one type of electrode layer is arranged as a multilayer structure, so that an identification degree of a touch signal is improved.

Abstract: This disclosure provides a memory device, a memory system, and an operation method. The memory device includes a memory array having a plurality of memory blocks and a control circuit coupled to the memory array and used to control the memory array. The control circuit is configured to determine a first average value of threshold voltages of bottom dummy cells in an unused memory block, determine a difference value between the first average value and a first reference value, and judge based on the difference value when bottom dummy cells in the memory block are to be programmed so that the first average value reaches a first threshold.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: A memory includes wordline (WL) layers and a controller coupled to the WL layers. The controller is configured to apply at least one verify voltage to a first WL layer of the WL layers during a verify phase, and apply a first pass voltage to a second WL layer of the WL layers during the verify phase. A first memory cell of the first WL layer is programmed before a second memory cell of the second WL layer. The first pass voltage is higher than a threshold voltage of a memory cell in a lowest programming state.

Abstract: An electrode assembly may comprise a positive electrode plate and a negative electrode plate, wherein a positive electrode active material layer of the positive electrode plate may comprise a positive electrode active material and a quinone compound; and a negative electrode active material layer of the negative electrode plate may comprise a negative electrode active material and a conductive polymer material, wherein based on the mass of the positive electrode active material layer, the mass content of the quinone compound mc % may be 0.5% to 3%; the capacity per gram of the quinone compound may be Capc; the capacity per gram of the positive electrode active material may be Cap; and based on the mass of the negative electrode active material layer, the mass content of the conductive polymer material may be mA %, satisfying the relationship of: 0 . 2 ? C ? a ? p C - Cap Cap × m C / m A ? 5 .

Abstract: A semiconductor device includes a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures in a first direction. The semiconductor device further includes a gate structure. The gate structure includes a top surface; a first sidewall angled at a non-perpendicular angle with respect to the top surface; and a second sidewall angled with respect to the top surface. The gate structure further includes a first horizontal surface extending between the first sidewall and the second sidewall, wherein the first horizontal surface is parallel to the top surface, and a dimension of the gate structure in a second direction, perpendicular to the first direction, is less than a dimension of each of the plurality of isolation structures in the second direction.

Abstract: An integrated circuit (IC) device includes first and second power rails extending in a first direction, a third power rail extending in the first direction between the first and second power rails, gate structures extending perpendicular to the first direction, each of two endmost gate structures extending continuously between endpoints underlying the first and second power rails, and first through fourth pluralities of active areas extending in the first direction between the endmost gate structures. Active areas of each of the first through fourth pluralities of active areas are aligned in the first direction, a first portion of the gate structures and first through fourth pluralities of active areas is configured as a functional circuit, and a second portion of the gate structures and first through fourth pluralities of active areas is configured as one of a decoupling capacitor or an antenna diode.

Abstract: Disclosed herein are tri-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a fin stack shaped as a fin extending away from a base, and a subfin dielectric stack. The fin includes a subfin portion and a channel portion, the subfin portion being closer to the base than the channel portion. The subfin dielectric stack includes a transistor dielectric material, and a fixed charge liner material disposed between the transistor dielectric material and the subfin portion of the fin.

Abstract: A disinfection system includes an ultraviolet disinfecting light, a controlling device, and an ultraviolet detecting device. The ultraviolet disinfecting light can be turned on or off under control. The controlling device controls the ultraviolet disinfecting light to be turned on or off. The ultraviolet detecting device is signally connected to the controlling device and is for detecting an intensity of the ultraviolet rays emitted by the ultraviolet disinfecting light. The controlling device controls the ultraviolet disinfecting light to increase an ultraviolet radiation dose of the ultraviolet rays emitted by the ultraviolet disinfecting light after the ultraviolet disinfecting light is turned on and the intensity of the ultraviolet rays is less than a predetermined intensity. An elevator equipment includes a car, a lift control device, and the disinfection system. In this way, the space can be disinfected with the ultraviolet rays to avoid insufficient disinfection effect.

Abstract: A distributed voltage clamping method for a 100% renewable-energy sending-end grid, including: selecting key nodes from the 100% renewable-energy sending-end grid, including their voltage levels and positions; installing a dynamic reactive power compensation device on each key node, where the dynamic reactive power compensation device is controlled by a constant alternating-current (AC) voltage effective value, and the instruction value of the constant AC voltage effective value is adjustable according to an operation mode; according to AC voltage variation of the sending-end grid under a typical working condition, judging whether the key nodes meet the checking requirements; if not, selecting more key nodes.

Abstract: A backup voltage and frequency support method for a 100%-renewable energy sending-end grid, including: (S1) selecting a plurality of support nodes in the 100%-renewable energy sending-end grid; (S2) mounting a backup voltage and frequency support device at each support node; and (S3) dynamically adjusting an active power output of a renewable energy station of the 100%-renewable energy sending-end grid according to a frequency of a grid-connection point.

Abstract: An image sensor including a semiconductor substrate, a plurality of color filters, a plurality of first lenses and a second lens is provided. The semiconductor substrate includes a plurality of sensing pixels arranged in array, and each of the plurality of sensing pixels respectively includes a plurality of image sensing units and a plurality of phase detection units. The color filters at least cover the plurality of image sensing units. The first lenses are disposed on the plurality of color filters. Each of the plurality of first lenses respectively covers one of the plurality of image sensing units. The second lens is disposed on the plurality of color filters and the second lens covers the plurality of phase detection units.