Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

Abstract: Provided is a method for performing relay forwarding on integrated access and backhaul (IAB) links. The method includes receiving, by a first IAB node, a data packet; and transmitting, by the first IAB node, the data packet to an IAB donor. Further provided are an information acquisition method, an IAB node, an IAB donor node and a storage medium.

Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

Abstract: A semiconductor element and a method for manufacturing the same are provided. The semiconductor element includes a plug and a via on the plug and electrically connected to the plug. The plug includes a tungsten plug and a conductive layer on the tungsten plug. The tungsten plug and the conductive layer include different materials. The tungsten plug has a first width in a lateral direction. The conductive layer has a second width in the lateral direction. The second width is greater than or equal to the first width. The conductive layer is between the via and the tungsten plug.

Abstract: A display panel that includes a pixel circuit including a plurality of refresh modes, and at least two refresh modes for the pixel circuit to be at different refresh frequencies, different reset signals corresponding to different reset signals.

Abstract: A positioning system and a positioning method based on radio frequency identification techniques (RFID) are provided. The positioning system includes in-vehicle devices, RFID readers and a server. The in-vehicle devices each includes a positioning device, an image capturing device and an image recognition module. The positioning device obtains a positioning location. The image capturing device captures a driving image. The image recognition module identifies adjacent vehicles, adjacent license plate information, and road attributes, and calculates relative location information. Each of the RFID readers reads a vehicle tag of one of the vehicles passing by, so as to mark a reference vehicle and generate reference vehicle information. A positioning adjustment module of the server determines whether the target vehicle is a reference vehicle, has been the reference vehicle or is a non-reference vehicle, and adjusts the positioning location of the target vehicle in different ways, accordingly.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: An abnormal traffic detection method is provided according to an embodiment of the disclosure. The method includes: obtaining network traffic data of a target device; sampling the network traffic data by a sampling window with a time length to obtain sampling data; generating, according to the sampling data, an image which presents a traffic feature of the network traffic data corresponding to the time length; and analyzing the image to generate evaluation information corresponding to an abnormal traffic. In addition, an abnormal traffic detection device is also provided according to an embodiment of the disclosure to improve a detection ability and/or an analysis ability for the abnormal traffic and/or a malware.

Abstract: Provided are an information transmission method and device. The method includes that: an Integrated Access and Backhaul Links (IAB) node transmits link information to a second IAB node, wherein the second IAB node is an IAB child node or an IAB parent node or an IAB donor. Also provided are an electronic device and a storage medium.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: A method of wireless communication is described. The method of wireless communication comprises receiving, by a first node of an integrated access and backhaul (IAB) network, resource information that includes resource availability information and/or resource configuration information; and transmitting, by the first node, the resource information to a second node.

Abstract: A method and apparatus for carrier aggregation is disclosed. In one embodiment, a method performed by a first wireless communication node, comprising: receiving a downlink signal containing first information from a second wireless communication node, and based on at least a portion of the first information, determining first resource information to perform sidelink communication between the first wireless communication node and at least one third wireless communication node.

Abstract: A backup voltage and frequency support method for a 100%-renewable energy sending-end grid, including: (S1) selecting a plurality of support nodes in the 100%-renewable energy sending-end grid; (S2) mounting a backup voltage and frequency support device at each support node; and (S3) dynamically adjusting an active power output of a renewable energy station of the 100%-renewable energy sending-end grid according to a frequency of a grid-connection point.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.

Abstract: The present disclosure provides a method for optimizing a liquid injection process of ionic rare earth ore, including the following steps of: 1) testing the hydraulic properties of an ore body; 2) determining the diffusion degree of the ore body; 3) determining the spatial distribution of the rare earth grade and the impurity grade of the ore body prior to leaching; 4) determining model parameters of competitive exchange of rare earth ions and impurity ions with ammonium ions; 5) obtaining distribution of rare earth ion concentration within the ore body after completion of leaching; 6) obtaining a profile plot of a rare earth leaching rate as a function of the concentration and dosage of an injected leaching agent; and 7) determining a minimum leaching agent dosage to achieve a target leaching rate according to the profile plot, and then determining the ammonium sulfate concentration according to the minimum leaching agent dosage.

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an H-like shape. The image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. The second isolation structure surrounds a second portion of the light-sensing region.

Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.