Patents by Inventor Ying Ji

Ying Ji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190203955
    Abstract: A heat source unit for a refrigeration apparatus, including: a casing; a heat exchanger disposed in an internal space of the casing, and that performs heat exchange between a refrigerant and air; a fan disposed in the internal space of the casing, and that horizontally blows out air passing through the heat exchanger; a first shut-off valve; and a second shut-off valve larger in diameter than the first shut-off valve; wherein the heat source unit further includes an above-shut-off-valves member disposed in the casing, positioned above the first shut-off valve and the second shut-off valve, and having at least one vertically penetrating wiring hole. The second shut-off valve is disposed below the first shut-off valve.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 4, 2019
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Keiko Kobayashi, Ying Ying Ji
  • Publication number: 20190011588
    Abstract: Simultaneous sources are separated with a deblending method wherein the fullband data deblended on a source-by-source basis. The fullband data is first decomposed into multiple subbands, and then a non-equispaced subband Radon transform is used to transform the decomposed data into the Radon domain. The deblending process is solved subband by subband by minimising a nonlinear objective function. The solution of the nonlinear objective function is found using a multi-step procedure.
    Type: Application
    Filed: December 19, 2016
    Publication date: January 10, 2019
    Inventors: Ying JI, Zijian TANG, Guido Jozef Maria BAETEN
  • Patent number: 9870982
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: January 16, 2018
    Assignee: Rambus Inc.
    Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
  • Patent number: 9822353
    Abstract: The present invention provides PEGylated aspartyl-tRNA synthetase (DRS) polypeptides, compositions comprising the same, and methods of using such polypeptides and compositions for treating or diagnosing a variety of conditions. The PEGylated DRS polypeptides of the invention have improved controlled release properties, stability, half-life, and other pharmacokinetic properties compared to non-PEGylated DRS polypeptides.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 21, 2017
    Assignee: aTyr Pharma, Inc.
    Inventors: Ying Ji Buechler, Chi-Fang Wu, Jeffrey Greve, John D. Mendlein
  • Patent number: 9816084
    Abstract: The present invention provides aspartyl-tRNA synthetase derived proteins (DRS polypeptides) with altered cysteine content, compositions comprising the same, and methods of using such polypeptides and compositions for treating or diagnosing a variety of conditions. The DRS polypeptides of the invention have immunomodulatory properties, and exhibit improved activity and stability.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 14, 2017
    Assignee: aTyr Pharma, Inc.
    Inventors: Ying Ji Buechler, Chi-Fang Wu, Ryan Andrew Adams, Kristi Helen Piehl, Jeffrey Greve, John D. Mendlein
  • Patent number: 9714419
    Abstract: The present invention provides PEGylated tyrosyl-tRNA synthetase (YRS) polypeptides, compositions comprising the same, and methods of using such polypeptides and compositions for treating or diagnosing a variety of conditions. The PEGylated YRS polypeptides of the invention have improved controlled release properties, stability, half-life, and other pharmacokinetic properties compared to non-PEGylated YRS polypeptides.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: July 25, 2017
    Assignee: aTyr Pharma, Inc.
    Inventors: Jeffrey D. Watkins, Ying Ji Buechler, Chi-Fang Wu, Minh-Ha Do, Alain P. Vasserot, John D. Mendlein
  • Patent number: 9688978
    Abstract: The present invention provides aspartyl-tRNA synthetase and Fc region conjugate polypeptides (DRS-Fc conjugates), such as DRS-Fc fusion proteins, compositions comprising the same, and methods of using such conjugates and compositions for treating or diagnosing a variety of conditions. The DRS-Fc conjugates of the invention have improved controlled release properties, stability, half-life, and other pharmacokinetic and biological properties relative to corresponding, unmodified DRS polypeptides.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: June 27, 2017
    Assignee: aTyr Pharma, Inc.
    Inventors: Ying Ji Buechler, Chi-Fang Wu, Ryan Andrew Adams, Jeffrey D. Watkins, John D. Mendlein
  • Publication number: 20170098595
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
    Type: Application
    Filed: October 3, 2016
    Publication date: April 6, 2017
    Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
  • Patent number: 9575196
    Abstract: Methods and apparatuses for processing seismic data to generate images or determine properties of an interior section of the Earth. The seismic data is processed to filter coherent noise such as ground roll noise from seismic survey data. The noise is attenuated using 3D and/or 2D fan filters, which may have combined low-pass and band-pass filters derived from signal decomposition. The filters are designed with selected operator length, velocity bands of signals and noises and frequency range for a primary trace and adjacent traces within the operator length. The data is decomposed with the filters into signals and noises, and the noises are then filtered from the decomposed data. The process may be repeated for various frequencies and traces within the seismic data. The methods may be used for surveys that have either regular or irregular seismic receiver or seismic source positions.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: February 21, 2017
    Assignee: WESTERNGECO L.L.C.
    Inventors: Ying Ji, Julian Edward Kragh, Ali Ă–zbek
  • Patent number: 9466568
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: October 11, 2016
    Assignee: Rambus Inc.
    Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
  • Patent number: 9449567
    Abstract: A method and a circuit component for suppressing crosstalk associated with the common voltage in a liquid crystal display are disclosed. In particular, in a liquid crystal display where the crosstalk is mainly caused by various control signals generated by a timing control circuit, one or more timing control signals are extracted from the timing control circuit and processed to become a compensation signal. The compensation signal is provided to display area of the liquid crystal display. The timing control signals generated by the timing control circuit include a start signal and a plurality of clock signals. The steps for processing these signals may include summing, inverting, high-pass filtering and amplitude adjustment, to be carried out in different orders and/or combinations. When the timing control signals are current signals, the steps for processing these signals may include current-to-voltage conversion, summing and inverting.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 20, 2016
    Assignee: AU Optronics Corporation
    Inventors: Ying-Ji Chen, Kun-Lang Wu, Chih-Wei Wu, Teng-Liang Yu, Wen-Chieh Huang
  • Publication number: 20160100486
    Abstract: A display module is provided including a display panel and an integrated circuit unit. The display panel is curved into a curved shape around a curvature axis and has a curved side, wherein the side also curves around the curvature axis. The integrated circuit unit is formed as a long stripe shape and has a first long side extending along an extending direction of the integrated circuit unit. The integrated circuit unit is directly or indirectly connected to the side, and the first long side extends along the extending direction of the curvature axis. Since the extending direction of the integrated circuit unit is aligned with the curvature axis, the integrated circuit unit will not be easily affected by the curvature of the display panel.
    Type: Application
    Filed: September 21, 2015
    Publication date: April 7, 2016
    Inventors: YING-JI CHEN, MEI-CHUN CHENG, TENG-LIANG YU, CHE-HAO YANG, CHIA-CHU WANG
  • Patent number: 9157762
    Abstract: Method and apparatus are provided to determine directional calibration parameters of an object. A method includes: disposing a tracking marker to the object, disposing the object on a calibration tool, rotating the object around its set linear axis while keeping the set linear direction unchanged, determining at least two three-dimensional rotation matrices of the tracking marker via a position tracking apparatus, and using the three-dimensional rotation matrices to determine the directional calibration parameters with the formula of two-point position relationship or rectilinear direction rotation relationship in the three-dimensional space. The action direction of the object is determined based on the determined directional calibration parameters and the current three-dimensional rotation matrix of the tracking marker.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: October 13, 2015
    Inventor: Ying Ji
  • Publication number: 20150221589
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
    Type: Application
    Filed: April 9, 2015
    Publication date: August 6, 2015
    Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
  • Patent number: 9091787
    Abstract: Generating an image of an interior of the Earth from a seismic survey using multiple sources. The multiple sources may be fired simultaneously and the data received by seismic sensors in the seismic survey may be decomposed so that seismic data generated by each of the multiple sources may be determined. Decomposing of the received data may be performed using frequency diverse basis functions and converting the data separation problem into an optimization problem, which can be a one-norm or zero-norm optimization problem in frequency-space domain. The decomposed data may be used to generate the image of the Earth's interior.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 28, 2015
    Assignee: WesternGeco L.L.C.
    Inventors: Ying Ji, Julian Edward Kragh, Philip A. F. Christie
  • Patent number: 9079839
    Abstract: Disclosed are methods for preparation of two pharmaceutical intermediates (I, II) of Aliskiren, said intermediates are obtained by reacting compound of formula I or II and tribromophosphorus oxide. The method replaces the method in the prior art which is using column chromatopraphy to produce the compounds I and II, and overcomes the defect that the method in the prior art hardly carry out in a large-scale industrial production. The product can be purified by recrystallization or vacuum distillation, and the chemical purity of the product is good.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: July 14, 2015
    Inventors: Xuezhi Yin, Bing Wang, Ying Ji, Mingyuan Liu
  • Publication number: 20150159148
    Abstract: The present invention provides PEGylated aspartyl-tRNA synthetase (DRS) polypeptides, compositions comprising the same, and methods of using such polypeptides and compositions for treating or diagnosing a variety of conditions. The PEGylated DRS polypeptides of the invention have improved controlled release properties, stability, half-life, and other pharmacokinetic properties compared to non-PEGylated DRS polypeptides.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 11, 2015
    Inventors: Ying Ji Buechler, Chi-Fang Wu, Jeffrey Greve, John D. Mendlein
  • Patent number: 9006907
    Abstract: An integrated circuit device is disclosed. The integrated circuit device includes a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces. The semiconductor die is formed with semiconductor devices, power supply circuitry coupled to the semiconductor devices, decoupling capacitance circuitry, and through-vias. The through-vias include a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the decoupling capacitance circuitry. Conductors are formed in a first metal layer disposed on the semiconductor die in accordance with a back-end semiconductor process. The conductors are configured to couple to the first and second groups of through-vias to establish conductive paths from the power supply circuitry to the decoupling capacitance circuitry.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Rambus Inc.
    Inventors: David Secker, Ling Yang, Chanh Tran, Ying Ji
  • Publication number: 20150066374
    Abstract: Performing seismic data processing using frequency diverse basis functions and converting a data processing problem into a one-norm or zero-norm optimization problem, which can be solved in frequency-space domain. The data processing problems can be data deghosting, data regularization or interpolation. The data being processed can be aliased or un-aliased, single sensor data or group-formed data, single component or multi-component data single source data or simultaneous sources, or some combinations.
    Type: Application
    Filed: April 3, 2013
    Publication date: March 5, 2015
    Inventors: Ying Ji, Julian Edward Kragh, Philip A. F. Christie
  • Patent number: 8965706
    Abstract: Adaptive filtering method to remove ground roll from seismic data. In an M channel adaptive filter, weights Wi are set using an adaptive algorithm based on seeking the minimum in the partial differential of cost function J. The cost function includes an expansion of the primary trace d into d=dg+?d (where: dg is ground roll contribution and ?d=dsig+dran, where dsig is the reflected signal component and dran is a random noise component) and a corresponding expansion of the reference x into x=xg+?x (where xg is ground roll contribution and ?x=xsig+xran; where xsig is a reflected signal component and xran is a random noise component). The delta components are included in the denominator of cost function J to provide an optimal solution of the filter coefficients biased by the reflection signal and random noise is removed.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: February 24, 2015
    Assignee: WesternGeco L.L.C.
    Inventor: Ying Ji