Patents by Inventor Ying-Ju Chen

Ying-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Supporting InFO Packages to Reduce Warpage
    Publication number: 20200013733
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Underfill Control Structures and Method
    Publication number: 20200006179
    Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Supporting InFO Packages to Reduce Warpage
    Publication number: 20200006251
    Abstract: A method includes encapsulating a first device die and a second device die in an encapsulating material, forming redistribution lines over and electrically coupling to the first device die and the second device die, and bonding a bridge die over the redistribution lines to form a package, with the package including the first device die, the second device die, and the bridge die. The bridge die electrically inter-couples the first device die and the second device die. The first device die, the second device die, and the bridge die are supported with a dummy support die.
    Type: Application
    Filed: July 5, 2018
    Publication date: January 2, 2020
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices
    Publication number: 20200006313
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Structure and Method of Forming a Joint Assembly
    Publication number: 20200006276
    Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • THREE-DIMENSIONAL INTEGRATED CIRCUIT STRUCTURES
    Publication number: 20190393159
    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Underfill control structures and method
    Patent number: 10515865
    Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Three-dimensional integrated circuit structures
    Patent number: 10504852
    Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE
    Publication number: 20190348366
    Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie CHEN, Ying-Ju CHEN, Hsien-Wei CHEN, Der-Chyang YEH, Chen-Hua YU
  • Semiconductor device
    Patent number: 10475760
    Abstract: A semiconductor device includes a substrate including a surface, a plurality of pads disposing on the surface of the substrate, the plurality of pads includes a non-solder mask defined (NSMD) pad and a solder mask defined (SMD) pad, and the NSMD pad is arranged at a predetermined location. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a solder mask over the surface of the substrate and the plurality of pads, forming a first recess in the solder mask to surround one of the plurality of pads, and forming a second recess in the solder mask and above one of the plurality of pads.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen, Tsung-Yuan Yu
  • Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same
    Publication number: 20190326259
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Mechanisms for Forming Post-Passivation Interconnect Structure
    Publication number: 20190326241
    Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20190295964
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first seal ring disposed over the molding, and a second seal ring disposed below the molding. The semiconductor structure further includes a first interconnect structure disposed below the first surface of the die and a second interconnect structure disposed over the second surface and the molding. The first seal ring is disposed in the second interconnect structure and disposed over the molding, and the second seal ring is provided within the die and the first interconnect structure.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: Ying-Ju CHEN, Hsien-Wei CHEN, Ming-Fa CHEN
  • RECOMBINANT BACULOVIRUSES AND THEIR USES IN DETECTING ARTHROPOD BORN VIRUS
    Publication number: 20190250161
    Abstract: Disclosed herein are recombinant baculoviruses suitable for detecting the presence of arthropod-borne viruses in a biological sample of a test subject. The information derived from the detection may also be used to render a diagnosis on whether the test subject is infected with the arthropod-borne viruses or not, so that proper course of treatment may be assigned to the subject.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Applicant: Chung Yuan Christian University
    Inventors: Tzong-Yuan WU, Szu-Cheng KUO, Pei-Yun SHU, Chang-Chi LIN, Der-Jiang CHIAO, Ying-Ju CHEN, Yi-Ting LIN, Shu-Fen CHANG, Chien-Ling SU
  • Redistribution layer structures for integrated circuit package
    Patent number: 10366953
    Abstract: An integrated circuit (IC) package with improved performance and reliability is disclosed. The IC package includes an IC die and a routing structure. The IC die includes a conductive via having a peripheral edge. The routing structure includes a conductive structure coupled to the conductive via. The conductive structure may include a cap region, a routing region, and an intermediate region. The cap region may overlap an area of the conductive via. The routing region may have a first width and the intermediate region may have a second width along the peripheral edge of the conductive via, where the second width may be greater than the first width. The intermediate region may be arranged to connect the cap region to the routing region.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Ying-Ju Chen
  • Devices employing thermal and mechanical enhanced layers and methods of forming same
    Patent number: 10347606
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Li-Hsien Huang, Chi-Hsi Wu, Der-Chyang Yeh
  • Mechanisms for forming post-passivation interconnect structure
    Patent number: 10340240
    Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Semiconductor structure and manufacturing method thereof
    Patent number: 10325865
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, an interconnect structure disposed over the die and the molding, and a first seal ring. The interconnect structure includes a dielectric layer and a conductive member disposed within the dielectric layer. The first seal ring is disposed within the dielectric layer and disposed over the molding.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • SEMICONDUCTOR STRUCTURE
    Publication number: 20190164925
    Abstract: A semiconductor structure including an insulating encapsulant, a plurality of semiconductor dies separately embedded in the insulating encapsulant, and an electrical communication path is provided. The electrical communication path includes at least one turning wiring connected to a conductive terminal of one of the semiconductor dies and extending across and above the insulating encapsulant to reach another conductive terminal of another one of the semiconductor dies. A layout area of the at least one turning wiring is within a region corresponding to an edge of one of the semiconductor dies and a closest edge of the adjacent one of the semiconductor dies.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME
    Publication number: 20190148276
    Abstract: In an embodiment, a package includes a first package structure including a first integrated circuit die having an active side and a back-side, the active side including die connectors, a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side and a back-side, the active side including die connectors, a routing die including die connectors bonded to the active sides of the first integrated circuit die and the second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die, an encapsulant encapsulating the first integrated circuit die, the second integrated circuit die, and the routing die, and a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the second integrated circuit die.
    Type: Application
    Filed: January 22, 2018
    Publication date: May 16, 2019
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen