Patents by Inventor Ying-Ju Chen

Ying-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package-on-package device with supplemental underfill and method for manufacturing the same
    Patent number: 9825008
    Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Ju Chen, Jie Chen, Hsien-Wei Chen
  • Package on-package method
    Patent number: 9812430
    Abstract: A method comprises forming a trench over a top surface of a metal structure of a bottom package, dispersing an epoxy flux material in the trench, mounting a top package on the bottom package, wherein a solder ball of the top package is in direct contact with the top surface of the metal structure and performing a reflow process to form a joint structure, wherein the joint structure comprises the solder ball of the top package coupled to the metal structure in the bottom package and an epoxy protection layer having a first edge in direct contact with a top surface of the bottom package and a second edge surrounding a lower portion of the solder ball.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Hsien-Wei Chen, An-Jhih Su, Ying-Ju Chen
  • PACKAGE-ON-PACKAGE DEVICE WITH SUPPLEMENTAL UNDERFILL AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20170317057
    Abstract: A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality of semiconductor packages on the precursor substrate, in which a gap is presented between the precursor substrate and each of the semiconductor packages; (ii) forming underfill material filling the gaps; (iii) cutting the precursor substrate along a region between adjacent ones of the semiconductor packages to form a plurality of discrete package-on-package devices; and (iv) applying supplemental underfill material to one of the package-on-package devices.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 2, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ying-Ju CHEN, Jie CHEN, Hsien-Wei CHEN
  • Strain reduced structure for IC packaging
    Patent number: 9806042
    Abstract: A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Tsung-Yuan Yu, Yu-Feng Chen, Tsung-Ding Wang
  • Light emitting diode bracket
    Patent number: 9806235
    Abstract: An LED bracket includes a first metal sheet, a second metal sheet and a casing. The casing covers the first and second metal sheets and includes a receiving slot. The casing partially covers the first and second metal sheets. The first metal sheet has a first pin terminal and a first carrying end. The second metal sheet has a second pin terminal and a second carrying end. The non-bent first and second pin terminals are opposite to each other and extended outwardly from the casing. The first and second carrying ends are disposed in the receiving slot and respectively have at least one first support portion and at least one second support portion to enhance the strength of fixing the first and second metal sheets with the casing. The non-bent pins improve the degree of freedom of the design of the casing and the light emission efficiency of LEDs.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: October 31, 2017
    Assignee: Unity Opto Technology Co., Ltd.
    Inventors: Ching-Huei Wu, Chih-Chao Chang, Ying-Ju Chen, Ping-Chen Wu
  • Semiconductor device and method of manufacture
    Patent number: 9793245
    Abstract: A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, An-Jhih Su, Jie Chen
  • Capacitor in post-passivation structures and methods of forming the same
    Patent number: 9786591
    Abstract: A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Hsien-Wei Chen, Hung-Yi Kuo, Tung-Liang Shao, Ying-Ju Chen, Tsung-Yuan Yu, Jie Chen
  • Semiconductor device and manufacturing method thereof
    Patent number: 9773745
    Abstract: A semiconductor device includes a substrate layer, a redistribution layer (RDL) disposed over the substrate layer, a conductive bump disposed over the RDL, and a molding disposed over the RDL and surrounding the conductive bump, wherein the molding includes a protruded portion laterally protruded from a sidewall of the substrate layer and away from the conductive bump.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Mechanisms for Forming Post-Passivation Interconnect Structure
    Publication number: 20170200687
    Abstract: Mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Devices Employing Thermal and Mechanical Enhanced Layers and Methods of Forming Same
    Publication number: 20170194292
    Abstract: A method includes attaching a first-level device die to a dummy die, encapsulating the first-level device die in a first encapsulating material, forming through-vias over and electrically coupled to the first-level device die, attaching a second-level device die over the first-level device die, and encapsulating the through-vias and the second-level device die in a second encapsulating material. Redistribution lines are formed over and electrically coupled to the through-vias and the second-level device die. The dummy die, the first-level device die, the first encapsulating material, the second-level device die, and the second encapsulating material form parts of a composite wafer.
    Type: Application
    Filed: March 2, 2016
    Publication date: July 6, 2017
    Inventors: Chen-Hua Yu, An-Jhih Su, Wei-Yu Chen, Ying-Ju Chen, Tsung-Shu Lin, Chin-Chuan Chang, Hsien-Wei Chen, Wei-Cheng Wu, Der-Chyang Yeh, Li-Hsien Huang, Chi-Hsi Wu
  • Underfill Control Structures and Method
    Publication number: 20170194226
    Abstract: A semiconductor device and method of reducing the risk of underbump metallization poisoning from the application of underfill material is provided. In an embodiment a spacer is located between a first underbump metallization and a second underbump metallization. When an underfill material is dispensed between the first underbump metallization and the second underbump metallization, the spacer prevents the underfill material from creeping towards the second underbump metallization. In another embodiment a passivation layer is used to inhibit the flow of underfill material as the underfill material is being dispensed.
    Type: Application
    Filed: March 2, 2016
    Publication date: July 6, 2017
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Method for enhancing collagen secretion and preventing cutaneous aging using chenopodium formosanum extract
    Patent number: 9687438
    Abstract: Provided is a method for enhancing collagen secretion and preventing cutaneous aging using Chenopodium formosanum extract. The Chenopodium formosanum extract includes active ingredients that are able to effectively enhance the ability of collagen secretion of dermal fibroblasts as well as prevent the glycation of collagen and resist the damage of ultraviolet light exposure. The preparation of the Chenopodium formosanum extract is environmental friendly and is able to promote the economic value of Chenopodium formosanum; thus, the present invention is suitable for applications in the development of food products, especially beverages, skin care and cosmetic products.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 27, 2017
    Assignee: TCI Co., Ltd.
    Inventors: Hsiang-Ling Su, Chin-Hsiu Yu, Ying-Ju Chen
  • Contact Pad for Semiconductor Devices
    Publication number: 20170179051
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.
    Type: Application
    Filed: March 3, 2017
    Publication date: June 22, 2017
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • Semiconductor Device and Method of Manufacture
    Publication number: 20170141080
    Abstract: A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, An-Jhih Su, Jie Chen
  • Semiconductor packaging device including via-in pad (VIP) and manufacturing method thereof
    Patent number: 9646941
    Abstract: A semiconductor device includes a carrier and a metallic structure including a metallic member, a pad and a via portion; wherein the metallic member is disposed inside the carrier, the pad is configured for receiving a solder bump and is disposed on a surface of the carrier, the via portion is configured for electrically connecting the metallic member and the pad, and the via portion is disposed proximal to an end of the pad. Further, a method of manufacturing a semiconductor device includes providing a carrier, removing a portion of the carrier for forming a via extending a surface of the carrier to an interior of the carrier, filling the via by a conductive material, and disposing the conductive material on the surface of the carrier, wherein the via is disposed proximal to an end portion of the conductive material.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Mechanisms for forming post-passivation interconnect structure
    Patent number: 9620469
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a contact pad over a substrate. The semiconductor device also includes a passivation layer over the substrate and a first portion of the contact pad, and a second portion of the contact pad is exposed through an opening. The semiconductor device further includes a post-passivation interconnect layer over the passivation layer and coupled to the second portion of the contact pad. In addition, the semiconductor device includes a bump over the post-passivation interconnect layer and outside of the opening. The semiconductor device also includes a diffusion barrier layer physically insulating the bump from the post-passivation interconnect layer while electrically connecting the bump to the post-passivation interconnect layer.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen
  • Semiconductor device including an embedded surface mount device and method of forming the same
    Patent number: 9589938
    Abstract: Embodiments of the present disclosure include devices and methods of forming the same. An embodiment is a device including a solder resist coating over a first side of a substrate, an active surface of a die bonded to the first side of the substrate by a first connector, and a surface mount device mounted to the die by a second set of connectors, the surface mount device being between the die and the first side of the substrate, the surface mount device being spaced from the solder resist coating.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen
  • Contact pad for semiconductor devices
    Patent number: 9589891
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ying-Ju Chen
  • Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices
    Publication number: 20170062401
    Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.
    Type: Application
    Filed: November 16, 2016
    Publication date: March 2, 2017
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Structure and method for package warpage control using dummy interconnects
    Patent number: 9570418
    Abstract: Presented herein is a package comprising a molding compound layer and an active device in the molding compound layer. A conductive via passes through the molding compound layer and is adjacent to the active device. A passivation layer is disposed on the molding compound layer. An active PPI is disposed on the passivation layer and is electrically connected to the conductive via. A dummy PPI is disposed on the passivation layer and is electrically isolated from the conductive via and the active device.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen