Patents by Inventor Ying-Lang Wang

Ying-Lang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • BSI Image Sensor Chips and Methods for Forming the Same
    Publication number: 20130153901
    Abstract: A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.
    Type: Application
    Filed: January 18, 2012
    Publication date: June 20, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Kei-Wei Chen, Ying-Lang Wang
  • Stressed semiconductor device and method of manufacturing
    Patent number: 8455883
    Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: June 4, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Miao-Cheng Liao, Min Hao Hong, Hsiang Hsiang Ko, Kei-Wei Chen, Ying-Lang Wang
  • Metal Shielding Layer in Backside Illumination Image Sensor Chips and Methods for Forming the Same
    Publication number: 20130134541
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Application
    Filed: March 14, 2012
    Publication date: May 30, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Semiconductor Device and Method of Formation
    Publication number: 20130126950
    Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.
    Type: Application
    Filed: November 23, 2011
    Publication date: May 23, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
  • Semiconductor device and method of formation
    Patent number: 8435893
    Abstract: A system and method for forming a semiconductor device is provided. An embodiment comprises forming a silicide region on a substrate along with a transition region between the silicide region and the substrate. The thickness of the silicide precursor material layer along with the annealing conditions are controlled such that there is a larger ratio of one atomic species within the transition region than another atomic species, thereby increasing the hole mobility within the transition region.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 7, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-Nan Nian, Li-Yen Fang, Yu-Ting Lin, Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
  • SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20130102152
    Abstract: A semiconductor manufacturing apparatus includes at least one inner retaining ring, and an outer retaining ring. The at least one inner retaining ring applies a first pressure to the polishing pad, and retains a substrate on the polishing pad. The outer retaining ring applies a second pressure to the polishing pad, and retains the at least one inner retaining ring on the polishing pad. Control of the first pressure is independent with respect to control of the second pressure.
    Type: Application
    Filed: October 20, 2011
    Publication date: April 25, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Chang CHAO, Kei-Wei CHEN, Ying-Lang WANG
  • METAL GATE STACK HAVING TIALN BLOCKING/WETTING LAYER
    Publication number: 20130075831
    Abstract: A metal gate stack having a TiAlN blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate; a work function layer disposed over the gate dielectric layer; a multi-function wetting/blocking layer disposed over the work function layer, wherein the multi-function wetting/blocking layer is a titanium aluminum nitride layer; and a conductive layer disposed over the multi-function wetting/blocking layer.
    Type: Application
    Filed: September 24, 2011
    Publication date: March 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiu-Ko JangJian, Szu-An Wu, Ying-Lang Wang, Chi-Wen Liu
  • SEMICONDUCTOR DEVICES UTILIZING PARTIALLY DOPED STRESSOR FILM PORTIONS AND METHODS FOR FORMING THE SAME
    Publication number: 20130049101
    Abstract: A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.
    Type: Application
    Filed: August 30, 2011
    Publication date: February 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen Chu HSIAO, Ju Wen HSIAO, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
  • Nickel Alloy Target Including a Secondary Metal
    Publication number: 20130020617
    Abstract: A target includes nickel and a secondary metal. The secondary metal has a volume percentage between about 1 percent and about 10 percent. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen
  • Apparatus for Wafer Grinding
    Publication number: 20130023188
    Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.
    Type: Application
    Filed: July 21, 2011
    Publication date: January 24, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
  • STRESSED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING
    Publication number: 20120292639
    Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.
    Type: Application
    Filed: May 19, 2011
    Publication date: November 22, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Miao-Cheng Liao, Min Hao Hong, Hsiang Hsiang Ko, Kei-Wei Chen, Ying-Lang Wang
  • VIA/CONTACT AND DAMASCENE STRUCTURES
    Publication number: 20120292768
    Abstract: A semiconductor structure is provided and includes a dielectric layer disposed over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is disposed in the opening.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 22, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Jung-Chih Tsao, Yu-Sheng Wang
  • CHEMICAL MECHANICAL POLISHING SLURRY, SYSTEM AND METHOD
    Publication number: 20120264303
    Abstract: A metal polishing slurry includes a chemical solution and abrasives characterized by a bimodal or other multimodal distribution of particle sizes or a prevalence of two or more particle sizes or ranges of particle sizes. A method and system for using the slurry in a CMP polishing operation, are also provided.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kei-Wei CHEN, Kuo-Hsiu WEI, Shih-Chieh CHANG, Ying-Lang WANG
  • SEMICONDUCTOR DEVICE
    Publication number: 20120241908
    Abstract: A semiconductor device is disclosed. The device includes a substrate; a first metal layer overlying the substrate; a dielectric layer overlying the first metal layer; and a second metal layer overlying the dielectric layer, wherein the first metal layer comprises: a first body-centered cubic lattice metal layer; a first underlayer, underlying the first body-centered cubic lattice metal layer, wherein the first underlayer is metal of body-centered cubic lattice and includes titanium (Ti), tungsten (W), molybdenum (Mo) or niobium (Nb); and a first interface of body-centered cubic lattice between the first body-centered cubic lattice metal layer and the first underlayer.
    Type: Application
    Filed: June 5, 2012
    Publication date: September 27, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Jung-Chih TSAO, Yu-Sheng WANG, Kei-Wei CHEN, Ying-Lang WANG
  • SEMICONDUCTOR DEVICE CONTACT STRUCTURES AND METHODS FOR MAKING THE SAME
    Publication number: 20120235299
    Abstract: A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.
    Type: Application
    Filed: March 16, 2011
    Publication date: September 20, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Chieh CHANG, Chih-Chung CHANG, Kei-Wei CHEN, Ying-Lang WANG
  • Via/contact and damascene structures and manufacturing methods thereof
    Patent number: 8247322
    Abstract: A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: August 21, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Jung-Chih Tsao, Yu-Sheng Wang
  • Current-leveling electroplating/electropolishing electrode
    Patent number: 8099861
    Abstract: A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: January 24, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Shih-Ho Lin, Chun-Chang Chen
  • Method and system for providing a selection of golden tools for better defect density and product yield
    Patent number: 8041440
    Abstract: Aspects of the present disclosure provide a method and a system for providing a selection of golden tools for better defect density and product yield. A golden tool selection and dispatching system is provided to integrate different components for robust golden tool selection and dispatching. The golden tool selection system selects a set of golden tools based on performance of a set of manufacturing tools and provides a fully automated operational environment to produce a product using the set of golden tools.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: October 18, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang Yung Cheng, Hsueh-Shih Fu, Ying-Lang Wang, Chin-Kun Wang
  • Oxygen plasma reduction to eliminate precursor overflow in BPTEOS film deposition
    Patent number: 7955993
    Abstract: A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O2 plasma.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: June 7, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin Kun Lan, Sheng-Wen Chen, Hung Jui Chang, Yu-Ku Lin, Ying-Lang Wang
  • CURRENT-LEVELING ELECTROPLATING/ELECTROPOLISHING ELECTRODE
    Publication number: 20100314256
    Abstract: A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.
    Type: Application
    Filed: August 11, 2010
    Publication date: December 16, 2010
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen, Shih-Ho Lin, Chun-Chang Chen