Patents by Inventor Ying-Lang Wang

Ying-Lang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9252180
    Abstract: A bonding pad structure for an image sensor device and a method of fabrication thereof. The image sensor device has a radiation-sensor region including a substrate and a radiation detection device, and a bonding pad region including the bonding pad structure. The bonding pad structure includes: an interconnect layer; an interlayer dielectric layer (IDL), both layers extending from under the substrate into the bonding pad region; an isolation layer formed on IDL; a conductive pad having a planar portion and one or more bridging portions extending perpendicularly from the planar portion, through the IDL and isolation layers, and to the interconnect layer; and a plurality of non-conducting stress-releasing structures disposed between the isolation layer and the conductive pad in such a way to adjoin its planar and the bridging portions together for releasing potential pulling stress applied thereon and preventing a conductive pad peeling.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Volume Chien, I-Chih Chen, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang
  • Patent number: 9224773
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 9224691
    Abstract: Semiconductor contact structures extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chieh Chang, Chih-Chung Chang, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20150367475
    Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 24, 2015
    Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
  • Publication number: 20150349251
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TING-CHANG CHANG, KUAN-CHANG CHANG, TSUNG-MING TSAI, CHIH-HUNG PAN, YING-LANG WANG, KEI-WEI CHEN, SHIH-CHIEH CHANG, TE-MING KUNG
  • Publication number: 20150349250
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.
    Type: Application
    Filed: May 28, 2014
    Publication date: December 3, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TING-CHANG CHANG, KUAN-CHANG CHANG, TSUNG-MING TSAI, CHIH-HUNG PAN, YING-LANG WANG, KEI-WEI CHEN, SHIH-CHIEH CHANG, TE-MING KUNG
  • Publication number: 20150311314
    Abstract: A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration.
    Type: Application
    Filed: June 19, 2015
    Publication date: October 29, 2015
    Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
  • Patent number: 9171759
    Abstract: A semiconductor wafer having a plurality of chip die areas arranged on a wafer in an array, each chip die area including a seal ring area with one or more first sets of polygonal structures. The wafer further comprises scribe line areas between the chip die areas, the scribe line areas including one or more second sets of polygonal structures. The presence of proximate polygonal structures between the scribe line and seal ring areas balance stresses between the chip die areas during wafer dicing operation.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Pin Cheng, Jung-Liang Chien, Chih-Kang Chao, Chi-Cherng Jeng, Hsin-Chi Chen, Ying-Lang Wang
  • Publication number: 20150279838
    Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Wen-Hsi Lee, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20150279880
    Abstract: A backside illuminated (BSI) image sensor device includes: a substrate including a front side and a back side; a multilayer structure over the back side; and a radiation-sensing region in the substrate. The radiation-sensing region is configured to receive a radiation wave entering from the back side and transmitting through the multilayer structure. The multilayer structure includes a first high-k dielectric layer, a metal silicide layer and a second high-k dielectric layer. The first high-k dielectric layer is located over the back side. The metal silicide layer is sandwiched between the first high-k dielectric layer and the second high-k dielectric layer.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: SHIU-KO JANGJIAN, CHUN CHE LIN, YU-KU LIN, YING-LANG WANG, CHUAN-PU LIU
  • Publication number: 20150262831
    Abstract: Methods for processing a substrate having a structure formed thereon and a system for processing a substrate are provided. A substrate is received from first processing equipment, where the first processing equipment has formed the structure on the substrate. A lithography process is performed on the received substrate. The lithography process includes exposing the substrate under an optical condition. The lithography process further includes polishing a backside of the substrate prior to the exposing of the substrate, where the polishing is configured to remove a topographical feature of the backside of the substrate or to remove a contaminant from the backside of the substrate. The substrate does not undergo a cleaning procedure during a period of time between i) the forming of the structure on the substrate, and ii) the exposing of the substrate.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: TANG-KUEI CHANG, KUO-HSIU WEI, KEI-WEI CHEN, HUAI-TEI YANG, YING-LANG WANG
  • Patent number: 9120194
    Abstract: A grinding wheel comprises an outer base with a first attached grain pad; and an inner frame with a second attached grain pad; and a spindle axis shared by the outer base and the inner frame, wherein at least one of the outer base and the inner frame can move independently along the shared spindle axis; and wherein the outer base, the inner frame, and the shared spindle axis all have a same center. A grinding system comprises an above said grinding wheel, and a wheel head attached to the shared spindle axis, capable of moving vertically, in addition to a motor driving the grinding wheel to spin; and a chuck table for fixing a wafer on top of the chuck table; wherein the grinding wheel overlaps a portion of the chuck table, each capable of spinning to the opposite direction of another.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Chun-Ting Kuo
  • Publication number: 20150235953
    Abstract: A semiconductor device and method of formation are provided. A semiconductor device includes a copper fill over a first layer in a first opening. The first layer includes cobalt and tungsten. A third layer including cobalt and tungsten is over the copper fill and the first layer. The first layer including cobalt and tungsten has a smoother sidewall than a first layer that does not have cobalt or tungsten. A smoother sidewall decreases defects in the copper fill, thus increasing conductivity of the copper fill. The first layer and the third layer reduce out diffusion of copper from the copper fill as compared to a semiconductor device that does not comprise such layers.
    Type: Application
    Filed: February 14, 2014
    Publication date: August 20, 2015
    Inventors: Jung-Chih Tsao, Chi-Cheng Hung, Yu-Sheng Wang, Shih-Chieh Chang, Wen-Hsi Lee, Ying-Lang Wang
  • Publication number: 20150214272
    Abstract: A backside illumination image sensor structure comprises an image sensor formed adjacent to a first side of a semiconductor substrate, wherein an interconnect layer is formed over the first side of the semiconductor substrate, a backside illumination film formed over a second side of the semiconductor substrate, a metal shielding layer formed over the backside illumination film and a via embedded in the backside illumination film and coupled between the metal shielding layer and the semiconductor substrate.
    Type: Application
    Filed: April 13, 2015
    Publication date: July 30, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiu-Ko JangJian, Chi-Cherng Jeng, Volume Chien, Ying-Lang Wang
  • Publication number: 20150206946
    Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.
    Type: Application
    Filed: October 31, 2014
    Publication date: July 23, 2015
    Inventors: I-CHIH CHEN, FU-TSUN TSAI, YUNG-FA LEE, KO-MIN LIN, CHIH-MU HUANG, YING-LANG WANG
  • Publication number: 20150200299
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih CHEN, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Patent number: 9070664
    Abstract: A device includes a substrate and a metal-oxide-semiconductor (MOS) device. The MOS device includes a gate dielectric over the substrate, a gate electrode over the gate dielectric, a source/drain region adjacent the gate dielectric, and a source/drain silicide over and contacting the source/drain region. The source/drain silicide comprises silicon, nickel, and a secondary metal. A ratio of a volume percentage of the secondary metal to a volume percentage of the silicon in the source/drain silicide is between about 0.005 and about 0.1. The secondary metal has a density between about 5,000 kg/m3 and about 15,000 kg/m3.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 30, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Ying-Lang Wang, Kei-Wei Chen
  • Patent number: 9064770
    Abstract: A method includes forming top metal lines over a semiconductor substrate, wherein the semiconductor substrate is a portion of a wafer having a bevel. When the top metal lines are exposed, an etchant is supplied on the bevel, wherein regions of the wafer sprayed with the etchant has an inner defining line forming a first ring having a first diameter. A trimming step is performed to trim an edge portion of the wafer, wherein an edge of a remaining portion of the wafer has a second diameter substantially equal to or smaller than the first diameter.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Patent number: 9064892
    Abstract: A semiconductor structure and method for forming the same provide a high mobility stressor material suitable for use as source/drain regions or other active devices. The structure is formed in a substrate opening and is doped with an impurity such as boron in upper portions but is void of the impurity in regions that contact the surfaces of the opening. The structure is therefore resistant to out-diffusion of the dopant impurity during high temperature operations and may be formed through selective deposition using reduced pressure chemical vapor deposition or reduced pressure epitaxial deposition.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: June 23, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen Chu Hsiao, Ju Wen Hsiao, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
  • Publication number: 20150170985
    Abstract: A semiconductor wafer includes a substrate, an integrated circuit and a die seal ring structure. The substrate is with a die region, a die seal ring region surrounding the die region and a scribe line region surrounding the die seal ring region. The substrate includes a first surface and a second surface opposite to the first surface, and periodic recesses within the first surface of the die seal ring region, the scribe line region or both the die seal ring region and the scribe line region. The integrated circuit is located on the first surface and the second surface of the die region. The die seal ring structure is located on the second surface of the die seal ring region. A semiconductor die is also provided.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 18, 2015
    Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
    Inventors: Hsi-Jung Wu, Volume Chien, Ying-Lang Wang, Hsin-Chi Chen, Ying-Hao Chen, Hung-Ta Huang