Patents by Inventor Ying Liang
Ying Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240139234Abstract: Provided herein is a potassium-binding polymer prepared by polymerization reaction of a monomer and a crosslinking agent, wherein the monomer is the compound of formula (V), the crosslinking agent is the compound of formula (VI), and/or the compound of formula (VII), wherein the variables are as defined in the specification; to the use thereof for treating or preventing hyperkalemia.Type: ApplicationFiled: November 4, 2021Publication date: May 2, 2024Applicant: WATERSTONE PHARMACEUTICALS (WUHAN) CO., LTD.Inventors: Min FU, Minglong HU, Tongtong LI, Ying LIANG, Xiaolong WANG, Yao YU, Faming ZHANG
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Patent number: 11969752Abstract: The present invention discloses an organic polymer film and a manufacturing method thereof. The organic polymer film is mainly manufactured by the following steps. Firstly, the step (A) provides a xylene precursor and a substrate, and the step (B) places the substrate inside of a plasma equipment. After that, the step (C) evacuates the plasma equipment while introducing a carrier gas which carries vapor of the xylene precursor, and the step (D) turns on a pulse power supply system of the plasma equipment, generating a short pulse for plasma ignition. Finally, the step (E) forms the organic polymer film on the substrate. In the aforementioned steps, the frequency of the short pulse plasma is between 1 Hz˜10,000 Hz, and the pulse period of the short pulse plasma is between 1 ?s˜60 ?s.Type: GrantFiled: December 17, 2021Date of Patent: April 30, 2024Assignee: FENG CHIA UNIVERSITYInventors: Ping-Yen Hsieh, Xuan-Xuan Chang, Ying-Hung Chen, Chu-Liang Ho
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Publication number: 20240133851Abstract: A fingerprint spectrum construction method for Xihuang capsules and a fingerprint spectrum includes: S1: taking contents of a Xihuang capsule, adding a methanol-chloroform-phosphoric acid solution, and carrying out ultrasonic extraction to obtain a Xihuang capsule test solution; S2: dissolving cholic acid, hyodeoxycholic acid, deoxycholic acid, bilirubin, muscone, and myrrhone in ethanol to obtain a mixed standard solution 1; dissolving quassin, 11-carbonyl-?-boswellic acid, 11-carbonyl-?-acetyl-boswellic acid, acetyl-11?-methoxy-?-boswellic acid, and sandaracopimaric acid in methanol to obtain a mixed standard solution 2; S3: respectively carrying out chromatography on the Xihuang capsule test solution and the mixed standard solutions 1 and 2, and recording corresponding chromatograms; and S4: constructing a fingerprint spectrum of the Xihuang capsule according to the chromatogram of the Xihuang capsule test solution and the chromatograms of the mixed standard solutions 1 and 2.Type: ApplicationFiled: January 14, 2024Publication date: April 25, 2024Inventors: Chengyuan LIANG, Changhua KE, Yanzi WANG, Yuting LIU, Xiuding YANG, Ying ZHOU, Jiaxuan LI
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Publication number: 20240136938Abstract: An AC-DC converter includes an AC voltage source, a rectifier, and a rectifier control circuit. The rectifier includes a field effect transistor (FET) having a source, a drain, and a gate. The drain of the FET is coupled to the AC voltage source, and the source is coupled to ground. The rectifier control circuit is coupled to the gate of the FET. The rectifier control circuit is configured to provide a ramp voltage to regulate the FET after the AC voltage source is turned off.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: Wenbo LIANG, Edward Er DENG, Ying LI, San Hwa CHEE
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Publication number: 20240101602Abstract: Provided is a peptide and method in preventing or treating infections caused by a wide spectrum of pathogens, including bacteria and fungus in hosts such as plants and animals. Methods of preventing or treating plant diseases and infection in animals are also provided.Type: ApplicationFiled: November 24, 2021Publication date: March 28, 2024Inventors: Rita P.Y. Chen, Chiu-Ping CHENG, Chien-Chih YANG, Kung-Ta LEE, Ying-Lien CHEN, Li-Hang Hsu, Hsin-Liang CHEN, Sung CHEN
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Publication number: 20240096998Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.Type: ApplicationFiled: November 21, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
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Publication number: 20240096707Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Ming-Chi Huang, Kuo-Bin Huang, Ying-Liang Chuang, Ming-Hsi Yeh
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Patent number: 11933103Abstract: A motorized window blind includes a top rail, a bottom rail, a plurality of slats assembled between the top rail and the bottom rail, and a control device received in the bottom rail so as to control movement of the slats. The control device includes a transmission unit, a motor, a first cord, a second cord and a power supply. The power supply provides electric power to the motor which is connected to the transmission unit. The first and second cords are respectively connected to the transmission unit, and extend through the slats, and are connected to the top rail. The transmission unit is driven by the motor to lift and lower the slats. The control device includes a detection unit and an angle detection member. The slats are lowered when the detection unit detects the power supply is low. The angle detection member angularly controls the salts status.Type: GrantFiled: September 30, 2020Date of Patent: March 19, 2024Assignee: CHING FENG HOME FASHIONS CO., LTD.Inventor: Wen Ying Liang
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Publication number: 20240088224Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: HSING-I TSAI, FU-HUAN TSAI, CHIA-CHUNG CHEN, HSIAO-CHUN LEE, CHI-FENG HUANG, CHO-YING LU, VICTOR CHIANG LIANG
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Publication number: 20240088147Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.Type: ApplicationFiled: January 9, 2023Publication date: March 14, 2024Inventors: XinYong WANG, Cun Cun CHEN, Ying HUANG, Chih-Liang CHEN, Li-Chun TIEN
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Publication number: 20240077062Abstract: A benchmark state space model construction method for an offshore wind turbine is provided. The benchmark state space model is constructed by the modal information of the first several orders of the high-order finite element model of the offshore wind turbine. Since the benchmark state space model is only established by the first several orders of the high-order finite element model, the time domain analysis of the offshore wind turbine using the benchmark state space model instead of the high-order finite element model can improve the calculation efficiency and reduce the calculation cost. The benchmark state space model construction method solves the problem of low computational efficiency and high computational cost of time domain analysis of offshore wind turbines using high-order finite element models due to the excessive number of high-order finite element units in existing technologies.Type: ApplicationFiled: August 23, 2023Publication date: March 7, 2024Applicant: Harbin Institute of Technology, ShenzhenInventors: Ying WANG, Jun LIANG
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Patent number: 11923201Abstract: Semiconductor device structures having metal gate structures with tunable work function values are provided. In one example, a first gate structure and a second gate structure formed on a substrate, wherein the first gate structure includes a first work function metal having a first material, and the second gate structure includes a second work function metal having a second material, the first material being different from the second material, wherein the first gate structure further includes a gate dielectric layer, a self-protective layer having metal phosphate, and the first work function metal on the self-protective layer.Type: GrantFiled: February 26, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Li Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11923428Abstract: A semiconductor device includes a fin structure disposed over a substrate. The semiconductor device includes a first interfacial layer straddling the fin structure. The semiconductor device includes a gate dielectric layer extending along sidewalls of the fin structure. The semiconductor device includes a second interfacial layer overlaying a top surface of the fin structure. The semiconductor device includes a gate structure straddling the fin structure. The first interfacial layer and the gate dielectric layer are disposed between the sidewalls of the fin structure and the gate structure.Type: GrantFiled: April 20, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Pan, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11887896Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.Type: GrantFiled: June 13, 2022Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
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Publication number: 20240026735Abstract: A scrolling mechanism for a window shade is received in a tube and includes a housing, a wheel, a driving gear, a bevel gear unit, a first scrolling unit and a second scrolling unit. Two springs are respectively connected to the first scrolling unit and the second scrolling unit. The driving gear drives the first scrolling unit, the first scrolling unit drives the second scrolling unit. The torque generated by the scrolling mechanism balances the torque that is created by operation to the bottom rail of the shade so as to control the position of the shade.Type: ApplicationFiled: August 29, 2022Publication date: January 25, 2024Inventor: WEN YING LIANG
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Publication number: 20240018827Abstract: A window shade adjustment device includes a top rail having two covers on two ends thereof, a housing located between the two covers and having a scrolling part located there. A shade is connected to the top rail and lifted or lowered along with rotation of the housing. Two end caps are respectively engaged with the two ends of the housing. Each end cap includes a tubular portion and a flange which extends radially therefrom. The flanges each are a ring-shaped part, and the thick of the flange is reduced from a center of the flange toward the periphery of the flange so as to form a ramp face that faces the housing. Multiple protrusions protrude axially from the ramp face of each of the flanges. When the shade moves upward and tilt, the shade moves along the ramp face and the protrusions which guide the shade not to tilt.Type: ApplicationFiled: August 29, 2022Publication date: January 18, 2024Inventor: WEN YING LIANG
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Publication number: 20230420534Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.Type: ApplicationFiled: January 12, 2023Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230420508Abstract: A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.Type: ApplicationFiled: June 24, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Pei Yun Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230420265Abstract: Disclosed is a method comprising: providing at least two structures with a metal layer over each; forming a patterned photolithographic layer over the metal layer over the first structure; removing the metal layer from the second structure via wet etch operations using a chemical etchant that is resistant to penetration into the photolithographic layer; and achieving, after wet etch operations, a remaining metal ratio of a distance X over a distance Y that is less than 179 and greater than 1, wherein X is the distance from a first line extending from an edge of the metal layer over the first structure to a second line extending from an edge of a channel region in the second structure, and Y is a second distance from the first line to a third line extending from an edge of the metal layer formed over the channel region in the first structure.Type: ApplicationFiled: June 22, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tefu Yeh, Cheng-Chieh Tu, Ming-Chi Huang, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230420543Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ling Chung, Chun-Chih Cheng, Ying-Liang Chuang, Ming-Hsi Yeh, Kuo-Bin Huang