Abstract: The invention provides a driving circuit applied in a LCD apparatus. The driving circuit includes N first channels, N second channels, 2N first switching units, and 2N second switching units. N is a positive integer and N?2. N second channels correspond to N first channels. When the driving circuit is operated under a first operation mode, N first switching units in the N first channels switch to connect with the corresponding N second channels, and the other N first switching units in the N second channels switch to connect with the corresponding N first channels according to a control signal respectively. N second switching units in the N first channels switch to connect with the corresponding N second channels, and the other N second switching units in the N second channels switch to connect with the corresponding N first channels according to a control signal respectively.

Abstract: A source driving circuit is disclosed. The source driving circuit includes a first integrated source driver and a second integrated source driver. The first integrated source driver includes a first receiving unit, a timing controller, a first source-driving-unit and a first transmission unit. The first receiving unit receives an original image data through a displayport (DP) interface, and decodes the original image data to a first display data and a second display data. The timing controller transmits a first control signal and a second signal. The first source-driving-unit receives the first control signal and the first display data. The first transmission unit receives the second display data, and the second integrated source driver receives the second control signal and the second display data, so as to elevate the compatibility between the source driver and the DP interface.

Abstract: The present invention discloses a timing controller including a driving signal generation module, a time-locking module, and a first logic circuit. The driving signal generation module generates a first isolation signal. The time-locking module detects whether or not all of a plurality of source driving units of a source driver lock a timing signal. The first logic circuit generates a second isolation signal, and adjusts the second isolation signal according to the output status of the first isolation signal. The gate driver selectively outputs a plurality of gate driving signals to a plurality of gate driving units of the gate driver according to the output status of the second isolation signal.

Abstract: A source driving circuit is disclosed. The source driving circuit includes a first integrated source driver and a second integrated source driver. The first integrated source driver includes a first receiving unit, a timing controller, a first source-driving-unit and a first transmission unit. The first receiving unit receives an original image data through a displayport (DP) interface, and decodes the original image data to a first display data and a second display data. The timing controller transmits a first control signal and a second signal. The first source-driving-unit receives the first control signal and the first display data. The first transmission unit receives the second display data, and the second integrated source driver receives the second control signal and the second display data, so as to elevate the compatibility between the source driver and the DP interface.

Abstract: A driving method is disclosed, and the driving method is applied into a liquid crystal display apparatus. The driving method includes steps as follows: receiving an original display data; rearranging the original display data to a new display data according to at least one scan driving mode; adjusting sequence of scan driving corresponding to the scan driving mode according to a sequence signal; transmitting the new display data to a display panel through data line, wherein sequence of the original display data corresponds to sequence of scan driving before adjusting, and sequence of the new display data corresponds to sequence of scan driving after adjusting according to the scan driving mode.

Abstract: A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.

Abstract: A method for transmitting image data in a display is provided. The method includes the steps of: sending first pixel data through a first bus to a source driver; sending second pixel data through a second bus to the source driver; reorganizing the first pixel data and the second pixel data in the source driver; and generating third pixel data according to the reorganization of the first pixel data and the second pixel data for channels in the source driver. A display is also disclosed herein.

Abstract: A driving method is disclosed, and the driving method is adopted to a liquid crystal display apparatus. The driving method includes steps as follows: receiving an original display data; rearranging the original display data to a new display data according to at least a scan driving mode; adjusting a sequence of scan driving so as to correspond to the scan driving mode according to a control signal; transmitting a new display data to a display panel through a data line, wherein the sequence of the original display data corresponds to the sequence of scan driving before adjusting, and a sequence of the new display data corresponds to the sequence of scan driving after adjusting according to the scan driving mode.

Abstract: A source driver adapted to drive a display panel is provided herein. The source driver includes a first output buffer, a detection module and a conversion module. The first output buffer enhances a first pixel signal and thereby outputs a first enhanced pixel signal. The detection module detects a rise time of the first enhanced pixel signal. The conversion module adjusts a driving capability of the first output buffer in response to the rise time for adjusting a slew rate of the first output buffer. Therefore, the first output buffer in the source driver can dynamically and automatically adjusts the slew rate of the first output buffer through a feedback mechanism composed of the detection module and the conversion module.

Abstract: The present invention discloses a timing controller including a driving signal generation module, a time-locking module, and a first logic circuit. The driving signal generation module generates a first isolation signal. The time-locking module detects whether or not all of a plurality of source driving units of a source driver lock a timing signal. The first logic circuit generates a second isolation signal, and adjusts the second isolation signal according to the output status of the first isolation signal. The gate driver selectively outputs a plurality of gate driving signals to a plurality of gate driving units of the gate driver according to the output status of the second isolation signal.

Abstract: The invention provides a driving circuit applied in a LCD apparatus. The driving circuit includes N first channels, N second channels, 2N first switching units, and 2N second switching units. N is a positive integer and N?2. N second channels correspond to N first channels. When the driving circuit is operated under a first operation mode, N first switching units in the N first channels switch to connect with the corresponding N second channels, and the other N first switching units in the N second channels switch to connect with the corresponding N first channels according to a control signal respectively. N second switching units in the N first channels switch to connect with the corresponding N second channels, and the other N second switching units in the N second channels switch to connect with the corresponding N first channels according to a control signal respectively.

Abstract: A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.

Abstract: A level shifter is disclosed and includes at least four Type 1 transistors and at least four Type 2 transistors. The sources of several Type 1 transistors are electrically connected to a first voltage terminal while the sources of several Type 2 transistors are connected to a second voltage terminal. The level shifter receive an input signal and outputs a logically equivalent output signal with higher voltage, wherein the voltage of the output signal is between the voltages of the first voltage terminal and the second voltage terminal.

Abstract: A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit.

Abstract: A driver unit comprises a latch circuit for holding digital image data in a voltage state, a digital-to-analog converter, and a voltage compensator circuit for raising the analog display voltage. The digital-to-analog converter can access content of the digital image data from the voltage state in the latch circuit, and convert the digital image data into analog display signals. In other embodiments, a method of driving a liquid crystal display comprises storing digital image data in a latch circuit under a voltage state, accessing a content of the digital image data from the voltage state held in the latch circuit, selecting a reference voltage according to the content of the digital image data for converting the digital image data into analog display signals, and raising the analog display voltage for obtaining a driving voltage.

Abstract: A source driver, an operation method thereof, and a flat panel display using the same are provided. The source driver includes a data channel, a switch and a switch controller. The data channel latches a pixel data according to timing of a line letch signal, and converts the latched pixel data to a driving signal for driving a display panel. The data channel decides a polarity of the driving signal according to a polarity signal. A first end of the switch is coupled to the data channel to receive the driving signal. The switch controller adjusts a pulse width of the line letch signal to obtain a control signal for controlling the switch according to the polarity signal. A pulse width of a first pulse is smaller than that of a second pulse in the control signal after the polarity signal is changed.

Abstract: A circuit for resetting a display having at least one driver outputting a driving voltage through an output channel to a corresponding data line of a panel comprises a first switch and a second switch. The first switch is actuated by a control pulse to transfer a reset voltage to the data line of the panel. The second switch is actuated by the control pulse to electrically isolate the output channel of the driver from the data line of the panel, wherein the control pulse is asserted during transient periods resulting from power-on and power-off of the display.

Abstract: A display device is provided, including a panel having a plurality of display cells, wherein the display cells are respectively connected to a plurality of data lines and gate lines. A plurality of source driver chips output a plurality of pixel signals to the data lines, wherein each source driver chip comprises a timing controller integrated therein for receiving an image control signal provided by a host and generating a plurality of timing control signals and the pixel signals according to-the image control signal. A gate driver chip outputs corresponding scan signals to the gate lines. A printed circuit board is also provided, and a plurality of transmission lines are routed on the printed circuit board and connected the source driver chips.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A readout apparatus and a multi-channel readout apparatus for a touch panel are provided to integrate different types of readout circuit. The readout apparatus set to a first mode reads the touch panel with a small amount of charges through an integrator. The readout apparatus set to a second mode reads a sensing current of a current type touch panel through a current to voltage converting unit and an inverting amplifier, so as to save a chip area. The multi-channel readout apparatus set to a third mode applies multiple channels to alternatively share an integrator to read the touch panel with a large amount of charges, so that an amount of feedback capacitors (integral capacitors) having a great area can be greatly reduced. Therefore, readout apparatus of the present invention can not only reduce a chip area, but can also be applied to various types of the touch panel.