Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor and a second transistor. The fingerprint capacitor CF has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR. The reference capacitor CS has a capacitance CS, and CFV<CS<CFR. The first transistor is configured to precharge the reference capacitor and the fingerprint capacitor during a precharge phase. The second transistor is configured to output the voltage of the reference capacitor during an evaluation phase. The precharge phase is controlled by a first readout select line, the evaluation phase is controlled by a second readout select line, the second readout select line is immediately next to the first readout select line, and the valid time to access the readout line is within an enabling period of the second readout select line.

Abstract: A wafer and a test method thereof are provided. The invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. The fingerprint capacitor CF has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR. The reference capacitor CS has a capacitance CS, and CFV<CS<CFR. The first transistor is configured to precharge the reference capacitor. The second transistor is configured to precharge the fingerprint capacitor. The third transistor is configured to redistribute the charges of the reference capacitor and fingerprint capacitor. The fourth transistor is configured to output the voltage of the reference capacitor after redistribution.

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.

Abstract: A wafer, a test system thereof, a test method thereof and a test device thereof are provided. The present invention utilizes a first group of probes to perform a high voltage stress (HVS) test on a first chip, and utilizes a second group of probes to perform a function test on a second chip, where a period of the high voltage stress test overlaps a period of the function test, thereby greatly decreasing the test time of the wafer.

Abstract: An operational amplifier circuit includes a control stage and an output stage. The control stage includes an analog control stage for generating a first control signal according to an input signal and a digital control stage for generating a second control signal according to the input signal. The output stage includes a sourcing circuitry coupled to the analog control stage and a load for sourcing a first current to the load according to the first control signal, and a sinking circuitry coupled to the digital control stage and the load for sinking a second current from the load according to the second control signal.

Abstract: Touch panels comprising a bias line biased at a bias voltage, a select line, a readout line, a photo cell and a readout circuit. The photo cell comprises a first photo switch, a second photo switch and a storage capacitor. The first photo switch and the storage capacitor is coupled in series between the readout line and the bias line, and the first photo switch is further controlled by the select line. The second photo switch is connected between the readout line and the bias line. The readout circuit and the select line are managed by a reset mode, an exposure mode and a readout mode. The voltage variation of output terminal of the readout circuit is used in obtaining the state of the photo cell.

Abstract: The invention relates to a signal driving system for a display. The signal driving system comprises: a signal controller, a flexible connector and a plurality of driving devices. The signal controller is used to produce a first control signal. The flexible connector is connected to the signal controller, and used to receive the first control signal. One of the driving devices is connected to the flexible connector. The driving devices connect in cascade. Each driving device comprises a data input port, a data output port and a driving signal output port. The data input port receives the first control signal or a second control signal. The data output port outputs the second control signal. According to the first control signal or the second control signal, the driving signal output port transmits a driving signal. The signal driving system of the invention can make the data output port of the driving device transmit the second control signal to the next driving device.

Abstract: A digital-to-analog converter (DAC) includes an R-2R ladder network, switches, and an operation amplifier (OP) with a feedback resistance, for providing an analog voltage in a positive polarity and a negative polarity. Each of the switches is switched between a connection to the OP and the reference voltage.

Abstract: The present invention relates to a data driving system and method for driving a panel. The data driving system comprises: a gamma voltage supply and a D/A converter. The gamma voltage supply produces a plurality of gamma voltages. The D/A converter receives the gamma voltages, a first pixel value and a second pixel value, and converts the first pixel value and the second pixel value to a corresponding gamma voltage in the gamma voltages. When the D/A converter converts the first pixel value, the gamma voltages have a first polarity offset. When the D/A converter converts the second pixel value, the gamma voltages have a second polarity offset. Because the data driving system of the invention periodically switches the first polarity offset and the second polarity offset of the gamma voltage supply, an offset in the driving voltage is eliminated by the first polarity (positive) offset and the second polarity (negative) offset in space and time. Therefore, there is no band mura in the panel.

Abstract: An output buffer and a controlling method are disclosed. The output buffer comprises an upper buffer and a lower buffer. In the controlling method, at first, a first voltage (V1) and a second voltage (V2) are applied on the upper buffer, and a third voltage (V3) and a fourth voltage (V4) are applied on the lower buffer, wherein V1>V2, V1>V4, V3>V2, and V3>V4. Then, the upper buffer is operated to output data to a plurality of pixels thereby operating the liquid crystals of the pixels over an upper supply range, wherein the upper supply range is from V1 to V2. Thereafter, the lower buffer is operated to output data to the pixels thereby operating the liquid crystals of the pixels over a lower supply range, wherein the lower supply range is from V3 to V4.

Abstract: A capacitive fingerprint sensor comprises a first transistor, a second transistor, a fingerprint capacitor and a third transistor. The fingerprint capacitor has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR, wherein CFV is smaller than CFR. The first transistor is configured to precharge the fingerprint capacitor. The second transistor is configured to discharge the fingerprint capacitor toward a bias voltage VB. The third transistor is configured to output the voltage of the fingerprint capacitor after discharge.

Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor and a second transistor. The fingerprint capacitor CF has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR. The reference capacitor CS has a capacitance CS, and CFV<CS<CFR. The first transistor is configured to precharge the reference capacitor and the fingerprint capacitor during a precharge phase. The second transistor is configured to output the voltage of the reference capacitor during an evaluation phase. The precharge phase is controlled by a first readout select line, the evaluation phase is controlled by a second readout select line, the second readout select line is immediately next to the first readout select line, and the valid time to access the readout line is within an enabling period of the second readout select line.

Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, an integrator, a first transistor, a second transistor and a third transistor. The fingerprint capacitor has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR, wherein CFV is smaller than CFR. The integrator has a reference capacitor Cfb. The first transistor is configured to control the fingerprint capacitor during a scan line period. The second transistor is configured to discharge the fingerprint capacitor. The third transistor is configured to precharge the fingerprint capacitor and to redistribute the charges between the fingerprint capacitor and the reference capacitor Cfb.

Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, an integrator, a first transistor, a second transistor and a multiplexer. The fingerprint capacitor has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR, wherein CFV is smaller than CFR. The integrator has a reference capacitor Cfb. The first transistor is configured to control the fingerprint capacitor during a scan line period. The second transistor is configured to precharge the fingerprint capacitor and to redistribute the charges between the fingerprint capacitor and the reference capacitor Cfb. The multiplexer is connected to the integrator for providing a first voltage VA and a second voltage VB, wherein the first voltage VA is greater than the second voltage VB.

Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor, a second transistor, a comparator and a multiplexer. The fingerprint capacitor has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR, wherein CFV is smaller than CFR. One end of the reference capacitor CS is connected to the fingerprint capacitor, and the other end is connected to a trigger signal, wherein the trigger signal is initiated only during a precharge phase. The first transistor is configured to control the fingerprint capacitor during a scan line period. The second transistor is configured to precharge the fingerprint and reference capacitors. One end of the comparator is connected to the second transistor. The multiplexer is connected to another input end of the comparator for providing a first voltage VA and a threshold voltage Vth.

Abstract: The present invention provides the voltage generator comprises providing a binary weight digital-to-analog converter (DAC) including an R-2R ladder network, and control switches, and an operation amplifier (OP) with a feedback resistance, and providing a plurality of voltages, from an input of said ladder network, in a positive polarity and a negative polarity, wherein said positive polarity and negative polarity are determined by a reference voltage, and each of said switches is switched between a connection to said OP and said reference voltage.

Abstract: A capacitive fingerprint sensor comprises a fingerprint capacitor, a reference capacitor, a first transistor, a second transistor, a third transistor and a fourth transistor. The fingerprint capacitor CF has a capacitance that is either a valley capacitance CFV or a ridge capacitance CFR. The reference capacitor CS has a capacitance CS, and CFV<CS<CFR. The first transistor is configured to precharge the reference capacitor. The second transistor is configured to precharge the fingerprint capacitor. The third transistor is configured to redistribute the charges of the reference capacitor and fingerprint capacitor. The fourth transistor is configured to output the voltage of the reference capacitor after redistribution.

Abstract: An optical sensor is disclosed. Each sensor pixel circuit of the optical sensor includes a first readout TFT for reading out voltage of a charge node, a second readout TFT for controllably resetting the charge node to a first reset voltage, and a photo TFT for discharging the voltage at the charge node to a second reset voltage in absence of an object(s).

Abstract: The present invention provides a programmable digital to analog converter comprises a reference voltage generator for generating a plurality of reference voltages based on a plurality of reference signals respectively, the gamma reference voltage generator comprising: a resistor string comprising a plurality of resistors in serial for providing a plurality of voltages; and a plurality of reference decoders, each receiving said voltages from said resistor string and selectively outputting a reference voltage from said voltages based on the corresponding reference signal, and a data decoder receiving the reference voltages for selectively outputting an analog voltage based on a data signal.