Abstract: An operational amplifier circuit includes an operational amplifier, an intermediate circuitry, and a control circuitry. The intermediate circuitry is coupled to a load. The operational amplifier is coupled to the intermediate circuitry and drives the load through the intermediate circuitry according to an input signal. The control circuitry is coupled to the intermediate circuitry and controls the intermediate circuitry to adjust an equivalent loading induced by the intermediate circuitry.

Abstract: An operational amplifier circuit includes an operational amplifier, a bias current provider, and a control circuitry. The operational amplifier drives a load according to an input signal. The bias current provider is coupled to the operational amplifier and provides a bias current to the operational amplifier. The control circuitry is coupled to the bias current provider and controls the bias current provider to adjust the bias current according to an operating status of the operational amplifier circuit.

Abstract: A voltage level shift circuit is provided. The circuit includes an input buffer unit, a level shift unit and a voltage stabilizing capacitor. The input buffer is coupled between a first voltage source and a first ground terminal. The level shift unit is coupled between a second voltage source and a second ground terminal. An input terminal of the level shift unit is coupled to an output terminal of the input buffer unit. The voltage stabilizing capacitor is coupled between the first voltage source and the second ground terminal. When a state transition occurs in the level shift unit, the voltage stabilizing capacitor maintains a voltage difference between the output terminal of the input buffer unit and the second ground terminal.

Abstract: An operational amplifier circuit includes an analog driving circuitry and a digital driving circuitry. The analog driving circuitry is coupled to a load and drives the load according to an input signal. The digital driving circuitry includes a code comparator, a sourcing unit, and a sinking unit. The code comparator compares a reference code with codes corresponding to the input signal and generates a first control signal and a second control signal accordingly. The sourcing unit is coupled to the code comparator and the load, and sources a first current to the load according to the first control signal. The sinking unit is coupled to the code comparator and the load, and sinks a second current from the load according to the second control signal.

Abstract: A data driver has several gamma-voltage generating circuits and several driving channels. The gamma-voltage generating circuits are used to process gamma-voltages of different colors. Each two groups of the driving channels are correspondingly coupled with the gamma-voltage generating circuit that generates a single color and is separately disposed at either side of the corresponding gamma generating circuit for outputting the gamma-voltages of the same color to a display panel.

Abstract: A wire-on-array (WOA) flat panel display is provided. The wire-on-array (WOA) flat panel display is characterized in a plurality of high input impedance components between the flexible printed circuit (FPC) board and the corresponding source driver circuits. Each of the high input impedance components is able to receive gamma voltages with little input current and then transmit the gamma voltages to each of the source driver circuit for production of source voltages of little banding effect.

Abstract: A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.

Abstract: A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.

Abstract: A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.

Abstract: The present invention discloses a signal interface to transmit a data signal to a driving circuit. The signal interface comprises a first circuit, a second circuit and a data bus. The first circuit comprises a first register. The second circuit comprises a selector, a second register, a receiver and a third register. If the data signal is a single-end signal, the first register and the selector receive the data signal. Then, the selector transmits the data signal to the second register. The data bus transmits the signal saved in the first register and the second register to the driving circuit. If the data signal is a serial signal, the selector receives and transmits the data signal to the receiver to have it transferred to a single-end signal. Then, the signal is transmitted to the third register and output via the data bus.

Abstract: An operational amplifier circuit includes an analog driving circuitry and a digital driving circuitry. The analog driving circuitry is coupled to a load and drives the load according to an input signal. The digital driving circuitry includes a code comparator, a sourcing unit, and a sinking unit. The code comparator compares a reference code with codes corresponding to the input signal and generates a first control signal and a second control signal accordingly. The sourcing unit is coupled to the code comparator and the load, and sources a first current to the load according to the first control signal. The sinking unit is coupled to the code comparator and the load, and sinks a second current from the load according to the second control signal.

Abstract: An operational amplifier circuit includes a control stage and an output stage. The control stage includes an analog control stage for generating a first control signal according to an input signal and a digital control stage for generating a second control signal according to the input signal. The output stage includes a sourcing circuitry coupled to the analog control stage and a load for sourcing a first current to the load according to the first control signal, and a sinking circuitry coupled to the digital control stage and the load for sinking a second current from the load according to the second control signal.

Abstract: An operational amplifier circuit includes an operational amplifier, an intermediate circuitry, and a control circuitry. The intermediate circuitry is coupled to a load. The operational amplifier is coupled to the intermediate circuitry and drives the load through the intermediate circuitry according to an input signal. The control circuitry is coupled to the intermediate circuitry and controls the intermediate circuitry to adjust an equivalent loading induced by the intermediate circuitry.

Abstract: An operational amplifier circuit includes an operational amplifier, a bias current provider, and a control circuitry. The operational amplifier drives a load according to an input signal. The bias current provider is coupled to the operational amplifier and provides a bias current to the operational amplifier. The control circuitry is coupled to the bias current provider and controls the bias current provider to adjust the bias current according to an operating status of the operational amplifier circuit.

Abstract: The present invention provides solutions to simplify and reduce the resources needed for manufacturing liquid crystal display modules. Failure of mid-process steps during mass production can result in significant costs. According to certain embodiments of the present invention, a WOA display panel architecture requires fewer LCM resources or has no PCB. Although the COG process and WOA method provide higher reliability in temporary LCD production, the costs associated with the space required for wires on the PCB or display panel for larger panel sizes remains expensive. Larger panel sizes also requires an increased number of driver ICs to construct a flat display panel. Similarly, the number of wires connecting each driver IC to a timing controller IC, gamma operational amplifier IC and DC-to-DC converter IC creates spacing problems that translate into higher production costs. These problems can be solved by certain embodiments of the present invention.

Abstract: A power saving method of a chip-on-glass liquid crystal display. The method first (a) wakes up the source drivers of the LCD and (b) transmitting the image data and control signals from the source driver corresponding to the FPC to the farthest waked source drivers, and then switching them to power-saving mode. Steps (b) and (c) are repeated until all the source drivers are switched to power-saving mode.

Abstract: A display implemented with a unique circuit arrangement. The display includes a glass substrate, a plurality of serial-connected source drivers and at least one gate driver. The source drivers and the at least one gate driver are disposed on the glass substrate using, for example, chip-on-glass technology. The display further includes at least one flexible connector, such as a flexible printed circuit board. Each of the at least one flexible connector corresponds to a selected one of the source drivers. The selected one of the source drivers is configured to receive image data and control information from the corresponded flexible connector, and convey the image data and the control information to at least one neighboring source driver.

Abstract: An identifier for identifying a source driver of a chip-on-glass liquid crystal display and an identifying method thereof are provided. The identifier includes a comparator for receiving a chip identity and a target identity, and generates a triggering signal to activate the source driver if the chip identity coincides with the target identity.

Abstract: A flat type display and method thereof capable of reducing power consumption includes a plurality of shift registers for temporarily storing digital image data, and a plurality of mode-selecting units for determining the shift registers not storing digital data, and then turning off corresponding output operational buffers based on the image resolution. Utilizing such flat type display and method, the power consumption of the flat type display is reduced due to the turning off of selected output operational buffers of the flat type display.

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.