Abstract: A method of processing a substrate that includes: exposing the substrate in a plasma processing chamber to a plasma powered by applying a first power to a first electrode of the plasma processing chamber for a first time duration; and after the first time duration, determining a process endpoint by: while exposing the substrate to the plasma by applying the first power to the first electrode, applying a second power to a second electrode of the plasma processing chamber for a second time duration that is shorter than the first time duration; and obtaining an optical emission spectrum (OES) from the plasma while applying the second power to the second electrode, where an energy of the second power over the second time duration is less than an energy of the first power over a sum of the first and the second time durations by a factor of at least 2.

Abstract: Some embodiments of the disclosure provide methods and systems for evaluating vegetation connectivity. In some embodiments, the disclosure provide a method including: acquiring vegetation patch vector data of a research area, extracting a geometric center from the vegetation patch vector data, and constructing the geometric center into a network node combination; constructing, according to a split-and-merge algorithm, the network node combination into Delaunay triangulation networks that are connected to but not overlap with each other; calculating and summarizing connectivity between a patch to which each node in the Delaunay triangulation network belongs and a patch to which an adjacent node belongs, to obtain overall connectivity between the patch to which each node belongs and the patch to which the adjacent node belongs; and performing spatial integrated expression processing on connectivity of each independent patch to obtain a spatial measurement result of vegetation connectivity of the research area.

Abstract: A method of processing a substrate that includes: exposing the substrate in a plasma processing chamber to a plasma powered by applying a first power to a first electrode of a plasma processing chamber; turning OFF the first power to the first electrode after the first time duration; while the first power is OFF, applying a second power to a second electrode of the plasma processing chamber for a second time duration, the second time duration being shorter than the first time duration, an energy of the second power over the second time duration is less than an energy of the first power over the first time duration by a factor of at least 2; and detecting an optical emission spectrum (OES) from species in the plasma processing chamber.

Abstract: A gamma tap circuit includes: (i) a first gamma division circuit configured to generate a first gamma tap voltage by performing voltage division of an upper gamma tap voltage and a lower gamma tap voltage, in-sync with a first clock signal CK1 and a first complementary clock signal CK1b, which is 180° out-of-phase relative to CK1, (ii) a second gamma division circuit configured to generate a second gamma tap voltage by performing voltage division of the upper gamma tap voltage and the first gamma tap voltage, in-sync with a second clock signal CK2 and a second complementary clock signal CK2b, which is 180° out-of-phase relative to CK2, and (iii) a third gamma division circuit configured to generate a third gamma tap voltage by performing voltage division of the first gamma tap voltage and the lower gamma tap voltage, in response to CK2 and CK2b, which have a lower frequency relative to CK1 and CK1b.

Abstract: An image sensor structure and a method of fabricating the structure are disclosed, in image sensor structure, at least one die is bonded to pixel substrate by bonding first bonding layer to second bonding layer, and the die includes signal processing circuit and/or storage device for photosensitive elements in pixel substrate. The die is bonded to the pixel substrate so that the signal processing circuit and/or storage device is/are coupled to photosensitive elements in pixel substrate. In this way, signal processing and/or storage functions of the image sensor can be provided without additional occupation of the area of the pixel substrate, allowing for more photosensitive elements to be arranged on the pixel substrate with the same area and thus resulting in a larger photosensitive area. Moreover, less wiring is needed on the 2D plane of the pixel substrate, helping in reducing interference with signals and delays and improving imaging quality.

Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.

Abstract: An object processing method includes: displaying a first operation interface in response to triggering a first operation control of a first stage of a target object, the first operation interface including at least one first operation item; displaying a content input interface in response to completing an operation for the at least one first operation item, the content input interface including at least one input item; in response to completion of content input for the at least one input item, determining a second target value and generating a second operation control corresponding to a second stage of the target object; displaying a second operation interface in response to triggering the second operation control, the second operation interface including at least one second operation item; and updating the state of the target object to a completed state in response to completing an operation for the second operation item.

Abstract: An organic light-emitting diode (OLED) display substrate, a manufacturing method thereof and a display panel are provided. The OLED display substrate has pixel regions and includes a base substrate and a pixel defining layer disposed on the base substrate; in regions of the pixel defining layer corresponding to the pixel regions, accommodation parts penetrating the pixel defining layer are disposed, and the pixel defining layer is further provided with guide parts disposed corresponding to the accommodation parts, the guide parts are located on a periphery of the corresponding accommodation parts and formed by recessed areas which are formed on a side of the pixel defining layer away from the base substrate, the recessed areas do not penetrate the pixel defining layer, and an orthographic projection of the guide part on the base substrate is directly coupled to an orthographic projection of the corresponding accommodation part on the base substrate.

Abstract: A memory device includes a first deck including a first set of word lines, a second deck including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first word line of the first set of word lines, apply a first pass voltage to a second word line of the second set of word lines while applying the program voltage to the first word line, and apply a second pass voltage to a third word line of the first set of word lines while applying the program voltage to the first word line. The third word line is between the first word line and the second word line. The second pass voltage is greater than the first pass voltage.

Abstract: A method of characterizing a plasma in a plasma processing system that includes: generating a pulsed plasma in a plasma processing chamber of the plasma processing system, the pulsed plasma being powered with a pulsed power signal, each pulse of the pulsed plasma including three periods: a overshoot period, a stable-ON period, and a decay period; performing cyclic optical emission spectroscopy (OES) measurements for the pulsed plasma, the cyclic OES measurements including: obtaining first OES data during one of the three periods from more than one pulses of the pulsed plasma; and obtaining a characteristic of the pulsed plasma for the one of the three periods based only on the first OES data.

Abstract: A photosensitive assembly includes a circuit board. The circuit board has a first surface, a second surface opposite to the first surface, and a first through hole extending through the first surface and the second surface. A photosensitive chip is disposed on the second surface. The photosensitive chip has a photosensitive area and a non-photosensitive area connected to the photosensitive area, the non-photosensitive area is electrically connected to one side of the second surface, and the photosensitive area is exposed from the first through hole. A reinforcing plate is disposed on the first surface. A thermal conductive layer is disposed on the photosensitive chip, and the thermal conductive layer includes a silica gel or a metal.

Abstract: A method and a platform for detecting an immunogenicity of a tumor neoantigen are provided. Specifically, the detection method includes the following steps: culturing human peripheral blood monocytes ex vivo for 13 days, adding an antigenic peptide fragment of human influenza virus and stimulating and activating cytokines, antigenic peptides, and immunoadjuvants during the 13 days, and finally conducting enzyme-linked immunospot (ELISPOT) chromogenic reaction and instrument-based scanning, counting, and analysis to detect the immunogenicity of tumor neoantigen. An application of the detection method and platform in biomedicine is provided. Compared with the prior art, the detection method and platform have advantages and characteristics of a short detection period, high convenience, low consumption of experimental cells, and low detection cost. Therefore, the detection method and platform can be used for ex vivo high-throughput assay for the immunogenicity of the tumor neoantigen.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming a multilayer film stack on the substrate; forming a supporter at a top of the multilayer film stack; and etching the multilayer film stack to form a plurality of gate structures arranged at intervals along a first direction, where the supporter penetrates a top of each of the plurality of gate structures and extends along the first direction.

Abstract: A semiconductor structure includes a substrate, wire structures, support structures and storage node contact structures. Each wire structure includes a wire and an isolation structure located on the wire. The wire structures extend along a first direction. The support structures are located on a side of the wire structures away from the substrate. The support structures are arranged at intervals in the first direction and connected with the isolation structures. The support structures extend along a second direction, and the second direction intersects with the first direction. The storage node contact structures are arranged in contact holes, and each of the contact holes is located within adjacent wire structures and adjacent support structures. A first air gap structure is provided between each of the storage node contact structures and a wire structure adjacent to the storage node contact structure.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, bit line structures distributed at intervals, initial support pattern structures distributed at intervals and target conductive contact structures. The bit line structures distributed at intervals are located on the substrate, and the bit line structures extend along a first direction. Each of the initial support pattern structures runs through top regions of the bit line structures, the initial support pattern structures extend along a second direction, and the first direction intersects with the second direction. Each of the target conductive contact structures is located within adjacent bit line structures and adjacent initial support pattern structures, and each of the target conductive contact structures includes a conductive plug structure and a target protective layer covering an outer sidewall of the conductive plug structure.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a base, where the base includes a memory array region and a peripheral circuit region around the memory array region; a plurality of buried bit lines disposed in the memory array region of the base; and at least one buried gate disposed in the peripheral circuit region of the base.

Abstract: Provided is an extension module for independently storing calibration data, including: a first interface, adapted to receive a first external input signal; a second interface, adapted to output the first output signal of the extension module; a signal processing circuit, connected between the first interface and the second interface; and a first memory, the first memory storing first calibration data, and the first calibration data being associated with the extension module. Furthermore, also provided is a component using the above extension module, and a component calibration method. On the one hand, the extension module of an embodiment may share an ADC sampling circuit on a main module, so that the manufacturing cost of the extension module is reduced. On the other hand, an embodiment can facilitate the replacement of different extension modules for the main module without repeated calibration.

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: generating a first operation command via one of a plurality of processing circuits, wherein the first operation command instructs to access a first memory group in a plurality of memory groups; and in response to a first state information, sending a first command sequence to the first memory group according to the first operation command to instruct the first memory group to perform an access operation. The first state information reflects a first activation state of the plurality of memory groups, and the first command sequence does not include a control command sequence configured to activate the first memory group.

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The memory management method includes: obtaining a first weight value corresponding to a first command in a command queue, wherein the command queue is used to store at least one command to be executed; obtaining a second weight value corresponding to at least one second command being executed; and in response to a sum of the first weight value and the second weight value being greater than a base value, delaying an execution of the first command.