Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a pair of transistors. The pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

Abstract: A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a first reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a cross-coupled pair of transistors. The cross-coupled pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.

Abstract: A phase shifter includes an active region, a first and a second set of gates and a set of contacts. The active region extends in a first direction and is located at a first level. The first and second set of gates each extend in a second direction, overlap the active region and are located at a second level. The second set of gates are positioned along opposite edges of the active region, are configured to receive a first voltage, and are part of a first transistor. The first transistor is configured to adjust a first capacitance of the phase shifter responsive to the first voltage. The set of contacts extend in the second direction, are over the active region, are located at a third level, and are positioned between at least the second set of gates.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.

Abstract: A voltage controlled oscillator (“VCO”) circuit is disclosed. The VCO includes a switch module comprising a first transistor and a second transistor; a first LC-tank module, the first LC-tank module is operatively connected between the drain of the first transistor and the drain of the second transistor; and a second LC-tank module, the second LC-tank module is operatively connected between the gate of the first transistor and the gate of the second transistor, the source of the first transistor and the source of the second transistor are operatively connected.

Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.

Abstract: A voltage controlled oscillator (“VCO”) circuit is disclosed. The VCO includes a switch module comprising a first transistor and a second transistor; a first LC-tank module, the first LC-tank module is operatively connected between the drain of the first transistor and the drain of the second transistor; and a second LC-tank module, the second LC-tank module is operatively connected between the gate of the first transistor and the gate of the second transistor, the source of the first transistor and the source of the second transistor are operatively connected.

Abstract: An amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.

Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.

Abstract: A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.

Abstract: An amplifier includes an input node, an output node, a transistor and a transformer. The input node is configured to receive a first signal. The output node is configured to output an amplified first signal. The transistor includes a first terminal, a second terminal and a third terminal. The first terminal is coupled to the input node and a first supply voltage source. The second terminal is coupled to a second supply voltage source and the output node. The third terminal is coupled to a reference node. The transformer is coupled to the first terminal and the third terminal. The transistor is configured to operate in a sub-threshold region and a near-triode region.

Abstract: An up-conversion mixer includes a mixer cell having at least one output node configured to generate an output. The up-conversion mixer further includes an input stage coupled to the mixer cell, the input stage configured to receive an input signal and to produce a local minimum in a third order harmonic of the output with respect to an input power. The up-conversion mixer further includes a power supply input configured to receive a power supply voltage and a ground, and a maximum number of transistor stages between the power supply input and the ground is two.

Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

Abstract: An inductor shielding structure includes a first conductive layer including a plurality of first conductive lines having a first width and a plurality of second conductive lines having a second width. The inductor shielding structure further includes a second conductive layer over the first conductive layer. The second conductive layer includes at least one third conductive line having a third width and a plurality of fourth conductive lines having a fourth width. Each conductive line of the at least one third conductive line is parallel to each conductive line of the plurality of first conductive lines. Each conductive line of the plurality of fourth conductive lines is parallel to each conductive line of the plurality of second conductive lines. The first width is different from the second width, or the third width is different from the fourth width.

Abstract: The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a VCO comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair.

Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and a first, second, third, and fourth inductive elements. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The first and second inductive elements are electrically coupled to the first output nodes, respectively. The third inductive element is electrically coupled to one of the second output nodes and DC-biased and magnetically coupled to the first inductive element. The fourth inductive element is electrically coupled to the other of the second output nodes and DC-biased and magnetically coupled to the second inductive element.

Abstract: An inductor shielding structure includes a first conductive layer including a plurality of first conductive lines having a first width and a plurality of second conductive lines having a second width. The inductor shielding structure further includes a second conductive layer over the first conductive layer. The second conductive layer includes at least one third conductive line having a third width and a plurality of fourth conductive lines having a fourth width. Each conductive line of the at least one third conductive line is parallel to each conductive line of the plurality of first conductive lines. Each conductive line of the plurality of fourth conductive lines is parallel to each conductive line of the plurality of second conductive lines. The first width is different from the second width, or the third width is different from the fourth width.