Abstract: The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal, The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract: The present invention relates to a semiconductor device and method for manufacturing the same. The semiconductor device includes a substrate, a dielectric layer, a metal layer, an interconnection metal and an insulation circular layer. The substrate has at least one through hole. The dielectric layer is disposed adjacent to the substrate. The metal layer is disposed adjacent to the dielectric layer. The interconnection metal is disposed in the at least one through hole. An insulation circular layer surrounds the interconnection metal, wherein the insulation layer has an upper surface and the upper surface contacts the dielectric layer. Whereby, the metal layer can be electrically connected to another surface of the substrate through the interconnection metal.

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: A semiconductor package structure and a package method thereof are provided. The semiconductor package structure includes a substrate, a sensing chip, a first patterned conductive layer and a electrical connection portion. The substrate has an accommodating portion, a first surface and a second surface opposite to the first surface. The accommodating portion are extended to the second surface from the first surface.

Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.

Abstract: A method for manufacturing a circuit board includes the following steps. First, a core layer is provided, wherein the core layer includes a first dielectric layer, and first and second metallic layers. A through hole is formed in the core layer. The core layer is disposed on a supporting plate, and an embedded component is disposed in the through hole, wherein the second metallic layer contacts the supporting plate, and the embedded component has at least one electrode contacting the supporting plate. The embedded component is mounted in the through hole. The supporting plate is removed. The first and second metallic layers are removed, and the thickness of the electrode of the embedded component is decreased. Third and fourth metallic layers are formed respectively, wherein the fourth metallic layer is electrically connected to the electrode of the embedded component. Finally, the third and fourth metallic layers are patterned so as to respectively form first and second patterned circuit layers.

Abstract: A semiconductor package and manufacturing methods thereof are provided. In one embodiment, the semiconductor package includes a die, a shield, a package body, and a redistribution layer. The die has an active surface and an inactive surface. The shield is disposed over the inactive surface of the die. The package body encapsulates the die and a first portion of the shield, where a first surface of the package body is substantially coplanar with the active surface of the die. The redistribution layer is disposed on the active surface of the die and on portions of the first surface of the package body.

Abstract: A package structure for connection with an output/input module is disclosed. The package structure can be applied to conventional multi-chip packages and system in packages. The package structure defines at least one insertion cavity that is vertically or horizontally disposed. By simply inserting an output/input module into the insertion cavity, an electrical connection can be established between the output/input module and the package structure. Accordingly, the package structure thus constructed can address the repairing, replacement and upgrading problems of electronic components encountered by a package structure that adopts the conventional soldering connection method.

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract: A semiconductor package structure and a package method thereof are provided. The semiconductor package structure includes a substrate, a sensing chip, a first patterned conductive layer and a electrical connection portion. The substrate has an accommodating portion, a first surface and a second surface opposite to the first surface. The accommodating portion are extended to the second surface from the first surface.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: A process of an embedded chip package structure includes following steps. Firstly, a metal core layer having a first surface, a second surface opposite to the first surface, an opening, and a number of through holes are provided. The opening and the through holes connect the first surface and the second surface. A chip is then disposed in the opening. Next, a dielectric layer is formed in the opening and the through holes to fix the chip in the opening. Thereafter, a number of conductive vias are respectively formed in the through holes and insulated from the metal core layer by a portion of the dielectric layer located in the through holes. A circuit structure is then formed on the first surface of the metal core layer by performing a build-up process, and the circuit structure electrically connects the chip and the conductive vias.

Abstract: A method for manufacturing a circuit board includes the following steps. First, a core layer is provided, wherein the core layer includes a first dielectric layer, and first and second metallic layers. A through hole is formed in the core layer. The core layer is disposed on a supporting plate, and an embedded component is disposed in the through hole, wherein the second metallic layer contacts the supporting plate, and the embedded component has at least one electrode contacting the supporting plate. The embedded component is mounted in the through hole. The supporting plate is removed. The first and second metallic layers are removed, and the thickness of the electrode of the embedded component is decreased. Third and fourth metallic layers are formed respectively, wherein the fourth metallic layer is electrically connected to the electrode of the embedded component. Finally, the third and fourth metallic layers are patterned so as to respectively form first and second patterned circuit layers.

Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.

Abstract: A package structure for connection with an output/input module is disclosed. The package structure can be applied to conventional multi-chip packages and system in packages. The package structure defines at least one insertion cavity that is vertically or horizontally disposed. By simply inserting an output/input module into the insertion cavity, an electrical connection can be established between the output/input module and the package structure. Accordingly, the package structure thus constructed can address the repairing, replacement and upgrading problems of electronic components encountered by a package structure that adopts the conventional soldering connection method.

Abstract: A package structure with an embedded capacitor, a fabricating process thereof and applications of the same are provided, wherein the package structure includes a dielectric layer, a first conductive layer, a second conductive layer, a first embedded plate and a second embedded plate. The dielectric layer has a thickness. The first conductive layer with a first potential is located on one side of the dielectric layer. The second conductive layer with a second potential is located on the dielectric layer at the other side thereof opposite to the first conductive layer. The first embedded plate and the second embedded plate that are embedded in the dielectric layer are separated at a distance, wherein the first embedded plate is electrically connected with the first conductive layer, and the second embedded plate is electrically connected with the second conductive layer.

Abstract: A substrate with an embedded passive element and methods for manufacturing the same are provided, wherein the substrate includes an interlayer circuit board having a first conductive circuit, a dielectric layer, a first electrode, a second electrode, and a second conductive circuit. The dielectric layer formed on the interlayer circuit board has a first recess and a second recess for respectively accommodating the first electrode and the second electrode. The embedded passive element is formed by the first electrode, the second electrode, and the dielectric layer between the first electrode and the second electrode. The second conductive circuit electrically connects the first electrode and the second electrode.

Abstract: A chip package structure including a circuit substrate, a chip, a heat sink, and at least one electrical connector is provided. The circuit substrate has a carrying surface and at least one contact disposed on the carrying surface. The chip is disposed on the carrying surface and electrically connected to the circuit substrate. The heat sink is disposed on the carrying surface and includes a thermal conductive body, at least one passive device, and at least one electrical conductive terminal. The thermal conductive body has a bonding surface and the passive device is embedded in the thermal conductive body. The electrical conductive terminal is connected to the passive device. The electrical connector is disposed between the electrical conductive terminal and the corresponding contact, such that the circuit substrate is electrically connected to the passive device. Since the passive device is disposed in the heat sink, the layout space is increased.