Abstract: A method for accessing memory and a memory device using the same method are provided. The method includes: coupling, by a first sense amplifier (SA) of a memory, to a memory cell of the memory to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the first SA; coupling a first command terminal of a system on chip (SoC) to a second terminal of the transistor, and coupling a first input/output (I/O) terminal of the SoC to a third terminal of the transistor; and issuing, by the SoC, an access command to the second terminal of the transistor to access the data output by the first SA through the third terminal of the transistor.

Abstract: A memory device includes at least one memory cell block, a first edge block, a second edge block, multiple first sense amplifiers, and multiple second sense amplifiers. The first edge block is coupled to multiple first word lines, where at least one of the first word lines receives an enabled first word line signal. The second edge block is coupled to multiple second word lines, where at least one of the second word lines receives an enabled second word line signal. The first sense amplifiers are disposed between the first edge block and the memory cell block. The second sense amplifiers are disposed between the second edge block and the memory cell block.

Abstract: A method for accessing memory and a memory device using the same method are provided. The method includes: coupling, by a first sense amplifier (SA) of a memory, to a memory cell of the memory to receive data from the memory cell; coupling a first terminal of a transistor of the memory to the first SA; coupling a first command terminal of a system on chip (SoC) to a second terminal of the transistor, and coupling a first input/output (I/O) terminal of the SoC to a third terminal of the transistor; and issuing, by the SoC, an access command to the second terminal of the transistor to access the data output by the first SA through the third terminal of the transistor.

Abstract: A pseudo static memory device includes multiple memories, an arbiter and a controller. The memories respectively generate multiple self-refresh request signals. Each of the self-refresh request signals indicates a time period for performing self-refresh operation of corresponding memory. The arbiter receives the self-refresh request signals and generates a latency synchronize flag during the memories being enabled. The controller decides an accessing latency for accessing the memories during an accessing operation according to the latency synchronize flag.

Abstract: A pseudo static memory device includes multiple memories, an arbiter and a controller. The memories respectively generate multiple self-refresh request signals. Each of the self-refresh request signals indicates a time period for performing self-refresh operation of corresponding memory. The arbiter receives the self-refresh request signals and generates a latency synchronize flag during the memories being enabled. The controller decides an accessing latency for accessing the memories during an accessing operation according to the latency synchronize flag.

Abstract: A bit data shifter receives an input signal and a plurality of clock signals. The bit data shifter includes a plurality of data shifter groups cascaded in sequence, and each of the plurality of data shifter groups cascaded in sequence includes a plurality of data latches cascaded in sequence and a master-slave flip-flop. The plurality of data latches cascaded in sequence is configured to delay the input signal in sequence based on the plurality of clock signals to generate a plurality of delayed signals. The master-slave flip-flop is configured to delay one of the plurality of delayed signals based on one of the plurality of clock signals to generate an input signal of a next data shifter group.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A random number generator is provided. The random number generator includes a linear feedback shift register and rotator. The linear feedback shift register is configured to provide a first pseudo-random number signal with a first value, wherein the first pseudo-random number signal includes a plurality of bits. The rotator is configured to shift and rotate the plurality of bits of the first pseudo-random number signal according to a signal to generate a second pseudo-random number signal with a second value. The second value is different from the first value.

Abstract: An integrated circuit and a detection method for multi-chip status thereof are provided. The integrated circuit includes at least one chip. The at least one chip has a stack status pin and a busy pin. The at least one chip applies a bias voltage on the busy pin according to a voltage status of the stack status pin. The at least one chip further detects an indication voltage on the busy pin, and decides whether a number of the at least chip is plural according to the indication voltage on the busy pin.

Abstract: A bit data shifter receives an input signal and a plurality of clock signals. The bit data shifter includes a plurality of data shifter groups cascaded in sequence, and each of the plurality of data shifter groups cascaded in sequence includes a plurality of data latches cascaded in sequence and a master-slave flip-flop. The plurality of data latches cascaded in sequence is configured to delay the input signal in sequence based on the plurality of clock signals to generate a plurality of delayed signals. The master-slave flip-flop is configured to delay one of the plurality of delayed signals based on one of the plurality of clock signals to generate an input signal of a next data shifter group.

Abstract: An integrated circuit and a detection method for multi-chip status thereof are provided. The integrated circuit includes at least one chip. The at least one chip has a stack status pin and a busy pin. The at least one chip applies a bias voltage on the busy pin according to a voltage status of the stack status pin. The at least one chip further detects an indication voltage on the busy pin, and decides whether a number of the at least chip is plural according to the indication voltage on the busy pin.

Abstract: A memory device is provided. The memory device includes a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller. The WL arbitrator receives a WL signal and segments the WL signal according to a burst length setting value, to obtain a segmented WL signal. In a synchronous mode, the refresh controller provides a first refresh trigger signal corresponding to the WL signal to refresh the PSRAM. In a smart refresh mode, the refresh controller provides a second refresh trigger signal corresponding to the segmented WL signal to refresh the PSRAM.

Abstract: A memory device is provided. The memory device includes: a memory cell array; a monitoring circuit, and an event-checking circuit. The monitoring circuit is configured to detect one or more event parameters of the memory cell array, wherein the one or more event parameters correspond to one or more interrupt events of the memory cell array. The event-checking circuit is configured to determine whether to assert an interrupt signal according to the one or more event parameters detected by the monitoring circuit. In response to the event-checking circuit determining to assert the interrupt signal, a processor handles the one or more interrupt events of the memory device according to the interrupt signal.

Abstract: A memory device is provided. The memory device includes a pseudo static random access memory (PSRAM), a word line (WL) arbitrator and a refresh controller. The WL arbitrator receives a WL signal and segments the WL signal according to a burst length setting value, to obtain a segmented WL signal. In a synchronous mode, the refresh controller provides a first refresh trigger signal corresponding to the WL signal to refresh the PSRAM. In a smart refresh mode, the refresh controller provides a second refresh trigger signal corresponding to the segmented WL signal to refresh the PSRAM.

Abstract: A random number generator is provided. The random number generator includes a linear feedback shift register and rotator. The linear feedback shift register is configured to provide a first pseudo-random number signal with a first value, wherein the first pseudo-random number signal includes a plurality of bits. The rotator is configured to shift and rotate the plurality of bits of the first pseudo-random number signal according to a signal to generate a second pseudo-random number signal with a second value. The second value is different from the first value.

Abstract: A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.

Abstract: A fuse array and a memory device are provided in the invention. The fuse array includes a plurality of fuses and a plurality of first D flip-flops. The fuses are configured to generate a plurality of data signals. Each of the first D flip-flops is respectively coupled to one corresponding fuse of the fuses to receive the data signal from the corresponding fuse and the first D flip-flops transmit a clock signal and the data signal to a plurality of second D flip-flops comprised in a plurality of memory cells. The first D flip-flops are connected in series and the second D flip-flops are connected in series.

Abstract: An e-fuse device includes a transferring circuit, a detecting-and-outputting circuit, and a fusing circuit. The transferring circuit transfers an input signal to a data node. The detecting-and-outputting circuit generates an output signal according to the logic level of the data node. The fusing circuit includes an e-fuse cell, a first transistor, a second transistor, and a switch element. The e-fuse cell is coupled between a high-voltage node supplied with the high voltage or a ground and a first node. The first transistor is coupled between the first node and a second node and is controlled by the output signal. The second transistor is coupled between the second node and the ground and is controlled by a fusing signal. The switch element is coupled between the first node and the data node and is controlled by a switch signal.

Abstract: An e-fuse device includes a transferring circuit, a detecting-and-outputting circuit, and a fusing circuit. The transferring circuit transfers an input signal to a data node. The detecting-and-outputting circuit generates an output signal according to the logic level of the data node. The fusing circuit includes an e-fuse cell, a first transistor, a second transistor, and a switch element. The e-fuse cell is coupled between a high-voltage node supplied with the high voltage or a ground and a first node. The first transistor is coupled between the first node and a second node and is controlled by the output signal. The second transistor is coupled between the second node and the ground and is controlled by a fusing signal. The switch element is coupled between the first node and the data node and is controlled by a switch signal.