Abstract: A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality of memory blocks. The memory controller outputs an access instruction and an access address to address the word lines for accessing the memory array, or the memory controller outputs a refresh instruction and a refresh address to address the word lines for refreshing the memory array, wherein the memory controller performs a refresh operation on each of the memory blocks corresponding to each of the word lines at predetermined intervals. The memory controller counts the number of times the access instructions have been output and determines whether that number equals a predetermined value or not. According to the determination result, the memory controller selects an address adjacent to the access address as the refresh address for the next refresh operation.

Abstract: A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal.

Abstract: A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal.

Abstract: A memory circuit is provided. The memory circuit includes a memory array, a plurality of word lines and a memory controller. The memory array has a plurality of memory blocks. The memory controller outputs an access instruction and an access address to address the word lines for accessing the memory array, or the memory controller outputs a refresh instruction and a refresh address to address the word lines for refreshing the memory array, wherein the memory controller performs a refresh operation on each of the memory blocks corresponding to each of the word lines at predetermined intervals. The memory controller counts the number of times the access instructions have been output and determines whether that number equals a predetermined value or not. According to the determination result, the memory controller selects an address adjacent to the access address as the refresh address for the next refresh operation.

Abstract: A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal.

Abstract: A control circuit, a memory device and a voltage control method thereof are provided. The memory device includes a memory cell, a voltage regulator circuit and the control circuit. The control circuit receives a clock signal, and determines a clock frequency of the clock signal so as to generate a control signal. An operation voltage is converted into an internal supply voltage for supplying the control circuit by the voltage regulator circuit according to the control signal.

Abstract: A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result.

Abstract: A random access memory and a refresh controller thereof are provided. The refresh controller includes a write action detector, a latch device, a reset circuit, and a refresh masking device. The write action detector is coupled to an address decoder of the random access memory, and is used to detect a write action in an address corresponding to the address decoder and generate a detection result. The latch device is coupled to the write action detector, and is used to receive and latch the detection result. The reset circuit is coupled to the latch device, receives a reset control signal, and resets the detection result according to the reset control signal. The refresh masking device is coupled to a corresponding word line control circuit and the latch device and is used to mask a refresh action on the word line control circuit according to the detection result.

Abstract: A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory chip, the respective internal address counter code is initially set according to the input address code and the respective selection signal.

Abstract: A memory device is provided. The memory device comprises a plurality of memory chips. The plurality of memory chips receive an input address code and alternately operate in an active mode. Each memory chip receives a selection signal and operates according to an internal address counter code. For each memory chip, the respective internal address counter code is initially set according to the input address code and the respective selection signal.

Abstract: A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indicates which mode the memory chip is operating at. The judgment circuit includes a detection unit and a sampling unit. The detection unit is coupled to a first voltage source and the option pad and further controlled by a control signal to generate at least one detection signal according to the current status of the option pad. The sampling unit samples the at least one detection signal after the control signal is asserted to generate the judgment signal. When the control signal is asserted, a level of the at least one detection signal is varied by a voltage provided by the first voltage source.

Abstract: A memory chip is provided. The memory chip operates at modes and includes an option pad and a judgment circuit. The judgment circuit is coupled to the option pad generates a judgment signal according to the current status of the option pad. The judgment signal indicates which mode the memory chip is operating at. The judgment circuit includes a detection unit and a sampling unit. The detection unit is coupled to a first voltage source and the option pad and further controlled by a control signal to generate at least one detection signal according to the current status of the option pad. The sampling unit samples the at least one detection signal after the control signal is asserted to generate the judgment signal. When the control signal is asserted, a level of the at least one detection signal is varied by a voltage provided by the first voltage source.

Abstract: A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read data from and write data to the selected wordline. A buffer of latches are coupled to the group of first sense amplifiers and have sufficient capacity to hold data corresponding to the selected wordline of memory cells.

Abstract: A method for refreshing a memory capacitor is provided. First, the refresh controller provides a refresh control signal. The pre-decoded row address counter counts and outputs a regular pre-decoded row address in response to the refresh control signal. The regular pre-decoded row address is inputted to the pre-decoded row address re-driver to obtain a row address. The memory capacitor in response to the row address is refreshed.

Abstract: A method for refreshing a memory capacitor is provided. First, the refresh controller provides a refresh control signal. The pre-decoded row address counter counts and outputs a regular pre-decoded row address in response to the refresh control signal. The regular pre-decoded row address is inputted to the pre-decoded row address re-driver to obtain a row address. The memory capacitor in response to the row address is refreshed.