Abstract: An immersion cooling system includes a receiving member, a heat dissipation channel, and a heat sink. The receiving member is filled with coolant. The receiving member is connected to an end of the heat sink, and heat-generating entities such as one or more servers are positioned in a cavity of the receiving member. The heat dissipation channel is connected to the cavity and is connected to the heat sink. The heat dissipation channel communicates with the cavity and allows circulation of the coolant in the channel, the heat sink cooling down the coolant flowing into heat dissipation channel from the cavity. The immersion cooling system is compact, occupies very little space, and is easily installed, maintained, and moved. A server system having the immersion cooling system is also disclosed.

Abstract: An immersion cooling system includes a receiving member, a heat dissipation channel, and a heat sink. The receiving member is filled with coolant. The receiving member is connected to an end of the heat sink, and heat-generating entities such as one or more servers are positioned in a cavity of the receiving member. The heat dissipation channel is connected to the cavity and is connected to the heat sink. The heat dissipation channel communicates with the cavity and allows circulation of the coolant in the channel, the heat sink cooling down the coolant flowing into heat dissipation channel from the cavity. The immersion cooling system is compact, occupies very little space, and is easily installed, maintained, and moved. A server system having the immersion cooling system is also disclosed.

Abstract: A printed circuit board (PCB) includes a top outer layer, a bottom outer layer, a signal transmission layer, an inner signal transmission layer, and a via system defined in the PCB. The via system includes two pairs of vias configured to transmit signals from a transmitter to a receiver. A signal transmission pathway is defined in the top outer layer, the signal transmission layer, and the inner signal transmission layer. Signals are sent from the transmitter to a first pair of vias, the signals are transmitted from the first pair of vias to a second pair of vias, and the signals are sent from the second pair of vias to the receiver. The two pairs of vias and the signal transmission pathway provide impedance matching to the signals.

Abstract: A printed circuit board (PCB) includes a top outer layer, a bottom outer layer, a signal transmission layer, an inner signal transmission layer, and a via system defined in the PCB. The via system includes two pairs of vias configured to transmit signals from a transmitter to a receiver. A signal transmission pathway is defined in the top outer layer, the signal transmission layer, and the inner signal transmission layer. Signals are sent from the transmitter to a first pair of vias, the signals are transmitted from the first pair of vias to a second pair of vias, and the signals are sent from the second pair of vias to the receiver. The two pairs of vias and the signal transmission pathway provide impedance matching to the signals.

Abstract: A capacitor includes a first patterned conductive layer, a second patterned conductive layer and a first patterned dielectric layer. The first patterned conductive layer resembles a comb with internal teeth, and the second patterned conductive layer resembles a comb with external teeth, the internal and the external teeth being interlaced in one plane. A thin first patterned dielectric layer within the same plane is shaped and arranged to infill all the gaps between the teeth. The first patterned conductive layer, the second patterned conductive layer, and the first patterned dielectric layer create a single coplanar layer, and a number of such interconnected coplanar layers are stacked within and contained by a multilayer circuit board.

Abstract: A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.

Abstract: A system and a method for ESD testing are contained in an ESD testing system which is running on an electronic device. A storage unit of the electronic device pre-stores a layout file which includes a layout pattern having electrical traces, an ESD entry point, and mounted positions of multiple electronic elements. The ESD testing method obtains the layout file from the storage unit; displays the layout pattern on a display unit of the electronic device, simulates ESD in the ESD entry point of the displayed layout pattern, tests electrical characteristics of the electrical traces between the ESD entry point and the mounted positions of multiple electronic elements to determine whether the electrical characteristics of the electrical traces pass or fail the ESD test, and marks the electrical traces which fail the ESD test on the displayed layout pattern.

Abstract: An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, and at least two resistors. When a signal transmitted by the circuit board is received by the input pins, a first portion of the signal is directly output from the output pins, a second portion of the signal is reflected by the first resistor and transmitted back to the output pins to output, and a third portion of the signal is reflected by the second resistor and transmitted back to the output pins to output, such that output of the equalizer applies two stages of compensation.

Abstract: In a computing device, a computerized method and a non-transitory storage medium are applied in checking whether the transmission lines in a stored wiring diagram meet a certain criterion in relation to vias in the routes of differential pairs. A transmission line is selected to determine whether or not the line belongs to a differential pair and passes through at least one via. Another transmission line of the differential pair is obtained for analysis when the selected transmission line passes through at least one via. Sizes of vias in the respective routes of the differential pair are compared and a distance between the vias of the differential pair is compared. The differential pair, and the sizes of vias which comply or do not comply with the criterion are recorded and displayed in a list of results.

Abstract: A capacitor includes a first patterned conductive layer, a second patterned conductive layer and a patterned dielectric layer. The first patterned conductive layer is interlaced with the second patterned conductive layer in one plane so as to present, within the smallest overall volume, the greatest surface area of one conductive layer in the closest proximity to the parts of the second conductive layer. The patterned dielectric layer is within a same plane as the first and second patterned conductive layers and in fills all gaps between the first and second patterned conductive layers to form a capacitor between the first and second conductive layers. The first and second patterned conductive layer and the patterned dielectric layer are stacked within and contained by a multilayer circuit board.

Abstract: A Marchand balun circuit includes a Marchand balun, an unbalanced matching circuit, and a balanced matching circuit. The Marchand balun includes an unbalanced terminal, and two balanced terminals. The unbalanced matching circuit includes a first and the second impedances which are connected between the unbalanced terminal and ground in series, and a first resistor which is connected between ground and a connection node of the first and the second impedances. The balanced matching circuit includes a third and a fourth impedances which are connected between one balanced terminal and ground in series, a fifth and a sixth impedance which are connected between the other balanced terminal and ground in series, a second resistor which is connected between ground and a connection node of the third and the fourth impedances, and a third resistor which is connected between ground and a connection node of the fifth and the sixth impedances.

Abstract: A FPCB includes a signal layer, a ground layer, and a dielectric layer lying between the signal layer and the ground layer. At least one high speed signal transmission line is formed on the signal layer. The ground layer has a copper-removed area corresponding to the transmission line. Two ground lines are symmetrically disposed at two opposite sides of the signal transmission line and substantially parallel to the signal transmission line, each ground line and the signal transmission line is spaced at a first predetermined distance. Each ground line and the signal transmission line are spaced at a first predetermined distance.

Abstract: In a computing device, a computerized method and a non-transitory storage medium are applied in checking a stored wiring diagram for high-noise components in close proximity to signal lines. An electronic component is selected in a PCB wiring file. A checking range of the selected electronic component is determined for searching for one or more signal transmission lines which pass within the checking range in the PCB wiring file. Basic information of the one or more signal transmission lines is recorded into a result list which is displayed on a display unit of the computing device.

Abstract: A capacitor includes a first patterned conductive layer, a second patterned conductive layer and a first patterned dielectric layer. The first patterned conductive layer resembles a comb with internal teeth, and the second patterned conductive layer resembles a comb with external teeth, the internal and the external teeth being interlaced in one plane. A thin first patterned dielectric layer within the same plane is shaped and arranged to infill all the gaps between the teeth. The first patterned conductive layer, the second patterned conductive layer, and the first patterned dielectric layer create a single coplanar layer, and a number of such interconnected coplanar layers are stacked within and contained by a multilayer circuit board.

Abstract: An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, and at least two resistors. When a signal transmitted by the circuit board is received by the input pins, a first portion of the signal is directly output from the output pins, a second portion of the signal is reflected by the first resistor and transmitted back to the output pins to output, and a third portion of the signal is reflected by the second resistor and transmitted back to the output pins to output, such that output of the equalizer applies two stages of compensation.

Abstract: A computing device and a method reads a circuit board layout file from a storage device, and selects a first signal transmission line from circuit board layout file as a target line. The computing device and method computes a distance between the target line and the aggressor line corresponding to each unit sample length. If the distance is more than or equal to a height of a sample region, the computing device and method defines the height of the sample region as a crosstalk space between the target line and the aggressor line corresponding to a unit sample length. Otherwise, if the distance is less than the height of the sample region, the computing device and method defines the distance as the crosstalk space between the target line and the aggressor line corresponding to the unit sample length.

Abstract: An equalizer includes a first delay module, a second delay module, a first amplitude module, a second amplitude module, and a combining unit. The first delay module receives a first signal and delays the first received signal for a preset period, and the first amplitude module transfers the first delayed signal to transmit a first weighted signal with a first peak amplitude. Similarly, the second delay module receives the first delayed signal and delays the second received signal for the preset period, and the second amplitude module transfers the second delayed signal to transmit a second weighted signal with a second peak amplitude. The combining unit combines an input signal and the first and the second weighted signals together to generate an equalized signal.

Abstract: A printed circuit board includes a base, a signal layer lying on the base, and a number of pairs of differential signal traces positioned on the signal layer. The base is made of a grid of glass fiber bundles filled with epoxy resin. Each pair of differential signal traces includes a first signal trace and a second signal trace. Each of the first and second signal traces extends in a zigzag pattern. The first signal trace includes a number of wave crests and wave troughs. The wave crests define a reference straight line that connects all the wave crest of the first signal trace. The ratio of the distance from each wave crest to the reference straight line to the orthogonal distance between each wave crest and an adjacent wave trough along the reference straight line is 1:5.

Abstract: A capacitor includes at least two electrode layers opposite to each other and a dielectric layer positioned between the at least two electrode layers. The at least two electrode layers have opposite polarities. Each electrode layer includes a positive electrode and a negative electrode. The positive electrode includes a plurality of first coupling portions spaced substantially evenly and arranged in parallel. The negative electrode includes a plurality of second coupling portions spaced substantially evenly and arranged in parallel. The positive electrode and the negative electrode of each electrode layer are coplanar, and the plurality of first coupling portions interlace with the plurality of second coupling portions.

Abstract: A method for setting a signal-equalizing system for use in an electronic device includes the following steps. Outputting a connection status of each channel and a number of misconnect options respectively associated with each channel to a display unit of the electronic device. Then, detecting whether at least one misconnect option is selected. If yes, determining a misconnected channel and adjusting the receiving setting for the receiving port of the misconnected channel to match with the transmitting setting for the transmitting port of the misconnected channel according to settings for each channel stored in the electronic device. The stored settings for each channel include a transmitting setting for the transmitting port of the channel and a receiving setting for the receiving port of the channel that matches the transmitting setting.