Patents by Inventor Ying-Wei Yen
Ying-Wei Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130072030Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.Type: ApplicationFiled: September 19, 2011Publication date: March 21, 2013Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen
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Patent number: 8394688Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.Type: GrantFiled: June 27, 2011Date of Patent: March 12, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang
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Publication number: 20130012012Abstract: A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer.Type: ApplicationFiled: July 10, 2011Publication date: January 10, 2013Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen, Shao-Wei Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh
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Publication number: 20130001707Abstract: A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Inventors: Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang, Chan-Lon Yang, Chin-Cheng Chien, Chun-Yuan Wu, Chih-Chien Liu, Chin-Fu Lin, Teng-Chun Tsai
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Publication number: 20120326162Abstract: A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer.Type: ApplicationFiled: June 27, 2011Publication date: December 27, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Liang LIN, Ying-Wei Yen, Yu-Ren Wang
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Publication number: 20120329261Abstract: A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen, Yu-Min Lin, Chin-Cheng Chien, Jei-Ming Chen, Chun-Wei Hsu, Chia-Lung Chang, Yi-Ching Wu, Shu-Yen Chan
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Publication number: 20120329285Abstract: A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas.Type: ApplicationFiled: June 22, 2011Publication date: December 27, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shao-Wei WANG, Chien-Liang Lin, Ying-Wei Yen, Yu-Ren Wang
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Publication number: 20120309171Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.Type: ApplicationFiled: May 30, 2011Publication date: December 6, 2012Inventors: Tsuo-Wen Lu, Wen-Yi Teng, Yu-Ren Wang, Gin-Chen Huang, Chien-Liang Lin, Shao-Wei Wang, Ying-Wei Yen, Ya-Chi Cheng, Shu-Yen Chan, Chan-Lon Yang
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Publication number: 20120306028Abstract: A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.Type: ApplicationFiled: May 30, 2011Publication date: December 6, 2012Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Chien-Liang Lin, Shao-Wei Wang, Ying-Wei Yen
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Publication number: 20120299124Abstract: A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.Type: ApplicationFiled: May 25, 2011Publication date: November 29, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Liang LIN, Gin-Chen Huang, Ying-Wei Yen, Yu-Ren Wang
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Publication number: 20120264284Abstract: A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds.Type: ApplicationFiled: April 14, 2011Publication date: October 18, 2012Inventors: Shao-Wei Wang, Ying-Wei Yen, Yu-Ren Wang, Chien-Liang Lin
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Patent number: 8263501Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.Type: GrantFiled: December 15, 2010Date of Patent: September 11, 2012Assignee: United Microelectronics Corp.Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
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Publication number: 20120193796Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.Type: ApplicationFiled: January 31, 2011Publication date: August 2, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
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Patent number: 8232605Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.Type: GrantFiled: December 17, 2008Date of Patent: July 31, 2012Assignee: United Microelectronics Corp.Inventors: Chien-Liang Lin, Yu-Ren Wang, Wu-Chun Kao, Ying-Hsuan Li, Ying-Wei Yen, Shu-Yen Chan
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Publication number: 20120156891Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.Type: ApplicationFiled: December 15, 2010Publication date: June 21, 2012Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Liang LIN, Yu-Ren Wang, Ying-Wei Yen
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Patent number: 7811892Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.Type: GrantFiled: March 31, 2006Date of Patent: October 12, 2010Assignee: United Microelectronics Corp.Inventors: Yun-Ren Wang, Ying-Wei Yen, Chien-Hua Lung, Shu-Yen Chan, Kuo-Tai Huang
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Publication number: 20100148271Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Inventors: Chien-Liang Lin, Yu-Ren Wang, Wu-Chun Kao, Ying-Hsuan Li, Ying-Wei Yen, Shu-Yen Chan
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Patent number: 7709316Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.Type: GrantFiled: August 15, 2008Date of Patent: May 4, 2010Assignee: United Microelectronics Corp.Inventors: Yun-Ren Wang, Ying-Wei Yen, Shu-Yen Chan, Kuo-Tai Huang
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Patent number: 7601404Abstract: A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping process of the next dose is performed on the dummy wafer. The nitrogen concentration of the chamber is thus adjusted rapidly to switch to the DPN process of the next dose. In addition, after several cycles of the above steps are repeated, a dummy wafer is inserted into the chamber, and a complete DPN process of the next dose is performed on the dummy wafer. This process is performed several times before switching to the next DPN process.Type: GrantFiled: June 9, 2005Date of Patent: October 13, 2009Assignee: United Microelectronics Corp.Inventors: Ying-Wei Yen, Yun-Ren Wang, Shu-Yen Chan, Chen-Kuo Chiang, Chung-Yih Chen
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Publication number: 20080318405Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.Type: ApplicationFiled: August 15, 2008Publication date: December 25, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Yun-Ren Wang, Ying-Wei Yen, Shu-Yen Chan, Kuo-Tai Huang