Abstract: A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate.

Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer is etched back to form spacers on the sidewalls of the gate structure. Finally, a source/drain region is formed in the substrate on each side of the spacer-coated gate structure.

Abstract: A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for repairing the nitrogen-doped gate dielectric layer. The above steps are carried out inside the same reaction chamber. Moreover, two or more wafers can be treated inside the reaction chamber at the same time.

Abstract: A method for fabricating a dielectric layer doped with nitrogen is provided according to the present invention. According to the method, a dielectric layer is formed on a semiconductor substrate. Two steps of nitridation processes are then performed on the dielectric layer. Following that, one step or two steps of annealing processes are performed on the dielectric layer. Dielectric layer formed by the method has uniform nitrogen dopant, and thus has fine electric properties.

Abstract: A method of fabricating a gate structure is provided. First, a sacrificial oxide layer is formed on a substrate. A nitridation treatment process is performed to redistribute the nitrogen atoms in the sacrificial layer and the substrate and produce a concentration profile such that the concentration of nitrogen progressively increases and then decreases toward the substrate with the maximum concentration of nitrogen in the sacrificial oxide layer. Next, the sacrificial oxide layer is removed. A re-oxidation process is performed to produce an interface layer on the surface of the substrate. A high K (dielectric constant) gate dielectric layer, a barrier layer and a metal layer are sequentially formed on the substrate. The metal layer, the barrier layer, the high K gate dielectric layer and the interface layer are defined to form a stacked gate structure.

Abstract: A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.

Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.

Abstract: A method for switching decoupled plasma nitridation (DPN) processes of different doses, which is able to decrease the switching time, is provided. According to the method, a dummy wafer is inserted into a chamber, a process gas introduced is ignited into plasma, and then a DPN doping process of the next dose is performed on the dummy wafer. The nitrogen concentration of the chamber is thus adjusted rapidly to switch to the DPN process of the next dose. In addition, after several cycles of the above steps are repeated, a dummy wafer is inserted into the chamber, and a complete DPN process of the next dose is performed on the dummy wafer. This process is performed several times before switching to the next DPN process.

Abstract: A method for fabricating a dielectric layer doped with nitrogen is provided according to the present invention. According to the method, a dielectric layer is formed on a semiconductor substrate. Two steps of nitridation processes are then performed on the dielectric layer. Following that, one step or two steps of annealing processes are performed on the dielectric layer. Dielectric layer formed by the method has uniform nitrogen dopant, and thus has fine electric properties.

Abstract: A method of manufacturing a metal-oxide-semiconductor transistor is provided. A substrate having a gate structure thereon is provided. A source/drain extension region is formed in the substrate on each side of the gate structure. Thereafter, a carbon-containing material layer is formed over the substrate and then the carbon-containing material layer is etched back to form spacers on the sidewalls of the gate structure. Finally, a source/drain region is formed in the substrate on each side of the spacer-coated gate structure.

Abstract: A method for forming a gate dielectric layer is described. A silicon oxide layer is formed on a semiconductor substrate. Then, a first and a second nitrogen doping processes are performed in sequence to the silicon oxide layer using plasma comprising inert gas and gaseous nitrogen to form a gate dielectric layer. The first nitrogen doping process is performed at a lower power, a lower pressure and a higher inert gas to nitrogen gas ratio than those at the second nitrogen doping process. The combination of the deeper nitrogen distribution of the first nitrogen doping process and the shallower nitrogen distribution of the second nitrogen doping process produces a flatter total nitrogen distribution profile so that leakage current from electron tunneling through the gate dielectric layer can be reduced.

Abstract: A method of fabricating a nitrogen-containing gate dielectric layer is described. First, a gate dielectric layer is formed on a substrate by performing a dilute wet oxidation process. Then, a nitridation step is performed for doping nitrogen into the gate dielectric layer. After that, a re-oxidation step is performed for repairing the nitrogen-doped gate dielectric layer. The above steps are carried out inside the same reaction chamber. Moreover, two or more wafers can be treated inside the reaction chamber at the same time.

Abstract: A chemical vapor deposition (CVD) system comprises a tubular furnace, at least one BTBAS supply piping line connected to a base portion of the tubular furnace, an exhaust piping line connected to an upper portion of the tubular furnace, a bypass line connecting the BTBAS supply piping line with the exhaust piping line, and a vacuum pump connected to the exhaust piping line, wherein the bypass line is initially interrupted. A batch of wafers is placed into a tube of the tubular furnace. Nitrogen-containing gas and carrier gas are flowed into the tube. BTBAS is flowed into the tube through the BTBAS supply piping line. A silicon nitride deposition process is then carried out in the tube to deposit a BTBAS-based silicon nitride film on the wafers. Upon completion of the silicon nitride deposition process, the BTBAS supply piping line is blocked and the initially interrupted bypass line is opened.

Abstract: A method for fabricating a semiconductor transistor device having ultra-shallow source/drain extensions is provided. A silicon substrate having thereon a poly gate structure is prepared. The poly gate structure has sidewalls and a top surface. An offset spacer is formed on its sidewall. An ion implantation process is carried out to form an ultra-shallow junction doping region in the silicon substrate next to the offset spacer. An oxide liner is deposited on the offset spacer and on the top surface of the poly gate structure. A tensile nitride spacer layer is then deposited on the oxide liner. A stress modification implantation process is performed to turn the tensile nitride spacer layer into a more compressive status. A dry etching process is then carried out to etch the nitride spacer layer so as to form a spacer.