Patents by Inventor Ying Wei

Ying Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND SYSTEMS FOR ESTIMATING BATTERY HEALTH
    Publication number: 20120310561
    Abstract: A method of estimating a state of health of a battery is disclosed. The method may include receiving information indicative of a history of electricity received by and discharged from the battery during a time period. The method may also include using the received information to estimate peaks in the electricity during the time period. Additionally, the method may include using an information processor to determine a parameter indicative of an estimated state of health of the battery based at least in part on an estimated magnitude of electricity at each of a plurality of the estimated peaks.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Inventors: Justin Dale Middleton, Benjamin Arthur Treichel, Wellington Ying-Wei Kwok, John Joseph Votoupal
  • SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF
    Publication number: 20120306028
    Abstract: A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided.
    Type: Application
    Filed: May 30, 2011
    Publication date: December 6, 2012
    Inventors: Yu-Ren Wang, Te-Lin Sun, Szu-Hao Lai, Po-Chun Chen, Chih-Hsun Lin, Che-Nan Tsai, Chun-Ling Lin, Chiu-Hsien Yeh, Chien-Liang Lin, Shao-Wei Wang, Ying-Wei Yen
  • GATE STRUCTURE AND A METHOD FOR FORMING THE SAME
    Publication number: 20120299124
    Abstract: A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang LIN, Gin-Chen Huang, Ying-Wei Yen, Yu-Ren Wang
  • FUSED THIOPHENES AS DUAL INHIBITORS OF EGFR/VEGFR AND THEIR USE IN THE TREATMENT OF CANCER
    Publication number: 20120295965
    Abstract: Disclosed are compositions and methods related to identification of modulators of EGFR and VEGFR.
    Type: Application
    Filed: December 16, 2010
    Publication date: November 22, 2012
    Inventors: Huayun Deng, Ye Fang, Ann MeeJin Ferrie, Mingqian He, Weijun Niu, Haiyan Sun, Elizabeth Tran, Ying Wei
  • CIRCUIT AND METHOD FOR CONTROLLING LEAKAGE CURRENT IN RANDOM ACCESS MEMORY DEVICES
    Publication number: 20120287739
    Abstract: A circuit for controlling leakage current in random access memory devices comprises a pre-charge equalization circuit. The pre-charge equalization circuit provides a pre-charge voltage to a pair of complementary bit lines of a memory cell of a random access memory device in accordance with a pre-charge signal. When the memory cell is in a self-refresh mode, the pre-charge signal is activated by a periodically triggered pre-charge request and also activated before and after the memory cell is self-refreshed.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 15, 2012
    Applicant: Elite Semiconductor Memory Technology Inc.
    Inventors: Chung Zen Chen, Ying Wei Jan, Jian Shiang Liang
  • MANUFACTURING METHOD FOR METAL GATE STRUCTURE
    Publication number: 20120264284
    Abstract: A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds.
    Type: Application
    Filed: April 14, 2011
    Publication date: October 18, 2012
    Inventors: Shao-Wei Wang, Ying-Wei Yen, Yu-Ren Wang, Chien-Liang Lin
  • Silicon dioxide film fabricating process
    Patent number: 8263501
    Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: September 11, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
  • POLYSILICON LAYER AND METHOD OF FORMING THE SAME
    Publication number: 20120193796
    Abstract: The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang Lin, Yun-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
    Patent number: 8232605
    Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: July 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Wu-Chun Kao, Ying-Hsuan Li, Ying-Wei Yen, Shu-Yen Chan
  • SILICON DIOXIDE FILM FABRICATING PROCESS
    Publication number: 20120156891
    Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 21, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Liang LIN, Yu-Ren Wang, Ying-Wei Yen
  • COATED, ANTIMICROBIAL, CHEMICALLY STRENGTHENED GLASS AND METHOD OF MAKING
    Publication number: 20120034435
    Abstract: The disclosure is directed to a chemically strengthened glass having antimicrobial properties and to a method of making such glass. In particular, the disclosure is directed to a chemically strengthened glass with antimicrobial properties and with a low surface energy coating on the glass that does not interfere with the antimicrobial properties of the glass. The antimicrobial has an Ag ion concentration on the surface in the range of greater than zero to 0.047 ?g/cm2. The glass has particular applications as antimicrobial shelving, table tops and other applications in hospitals, laboratories and other institutions handling biological substances, where color in the glass is not a consideration.
    Type: Application
    Filed: August 3, 2011
    Publication date: February 9, 2012
    Inventors: Nicholas Francis Borrelli, David Lathrop Morse, Wageesha Senaratne, Florence Verrier, Ying Wei
  • Method of making a three dimensional cell culture matrix
    Patent number: 8080418
    Abstract: This invention relates three dimensional porous cell culture matrices or scaffolds which have directional porous structure. More particularly, this invention relates to three dimensional porous cell culture matrices or scaffolds for cell culture which are derived from or contain gums including naturally occurring gums, plant gums, galactomannan gums or derivatives thereof. The invention also relates to methods of making the matrices, articles of manufacture (e.g., cell culture vessels and labware) having such matrices or scaffolds, methods of applying these materials to cell culture surfaces, and methods of using cell culture vessels having these three dimensional porous cell culture matrices or scaffolds.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: December 20, 2011
    Assignee: Corning Incorporated
    Inventors: Frederick E. Noll, Wageesha Senaratne, Ying Wei
  • MITOCHONDRIA KATP ION CHANNEL AS A DRUG TARGET FOR PREVENTING LIVER DISEASES AND METHODS TO SCREEN MITOCHONDRIA KATP MODULATORS
    Publication number: 20110246078
    Abstract: Disclosed are compositions and methods related to modulation of KATP channels and methods of treating liver disorders by modulating KATP and mito-KATP channels.
    Type: Application
    Filed: March 23, 2011
    Publication date: October 6, 2011
    Inventors: Ye Fang, Joydeep Lahiri, Haiyan Sun, Ying Wei
  • AQUEOUS LUBRICANT EMULSION FOR MEDICAL OR APPARATUS AND A METHOD OF WASHING
    Publication number: 20110190179
    Abstract: An aqueous lubricant emulsion for medical or food apparatus, comprising: (a) 5 wt % to 30 wt % of a mineral oil; (b) 5 wt % to 30 wt % of an emulsifier system consisting of two emulsifiers selected from the group consisting of sorbitan fatty acid ester, polyoxyethylene sorbitan fatty acid ester, oleyl alcohol ether, triethanolamine oleate, wherein the mass ratio of the two emulsifiers is in a range of 2:8 to 8:2; (c) 0.5 wt % to 5 wt % of one or more coemulsifiers selected from the group consisting of fatty alcohols, long-chain fatty acids, and diisooctyl succinate sulfonates; and (d) the balance of water. A method for washing medical or food apparatus including the step of subjecting the medical or food apparatus to a treatment using the lubricant emulsion according to the invention after a washing step for the medical or food apparatus is also described.
    Type: Application
    Filed: June 19, 2009
    Publication date: August 4, 2011
    Inventors: Ying Wei Xie, Xiaolei Jia
  • Semiconductor device
    Patent number: 7902673
    Abstract: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: March 8, 2011
    Assignee: United Microelectronics Corp.
    Inventor: Ying-Wei Wang
  • METHOD FOR ESTIMATION OF IMAGE DEFOCUS AND DEFOCUS RESTORATION
    Publication number: 20110032575
    Abstract: A method for determining local defocus distance in a scanned image of a non-planar original object is provided comprising scanning at least a portion of the non-planar original object to produce first scanned image data at a first focal plane and scanning same the at least a portion of the non-planar original object to produce at least second scanned image data at a second focal plane. The first scanned image data is different from the second scanned image data wherein a distance between the first focal plane and the second focal plane is a predetermined quantity. The method further comprises estimating an out-of-focus distance of the object from the first and the second scanned image data.
    Type: Application
    Filed: August 6, 2009
    Publication date: February 10, 2011
    Applicant: Xerox Corporation
    Inventors: Beilei Xu, Robert Paul Loce, Chu-heng Liu, Ying-wei Lin
  • Multi-step annealing process
    Patent number: 7811892
    Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: October 12, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Ren Wang, Ying-Wei Yen, Chien-Hua Lung, Shu-Yen Chan, Kuo-Tai Huang
  • Reducing power consumption in multiprocessor systems
    Patent number: 7779287
    Abstract: Techniques that may be utilized in a multiprocessor system to reduce power consumption are described. In one embodiment, one or more internal components of a processor core are clocked at least partially by a frequency controlled clock signal.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: August 17, 2010
    Assignee: Intel Corporation
    Inventors: Soon Chieh Lim, Loo Shing Tan, Ying Wei Liew
  • TOOLING METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED THEREOF
    Publication number: 20100155948
    Abstract: A tooling method for fabricating semiconductor devices includes identifying two adjacent device lines having a device-to-device spacing width in an active region of a substrate, performing an operation to selectively define a first region as a region between the two adjacent device lines overlapping the active region, forming a first block pattern corresponding to the first region on a photomask when the device-to-device spacing width is equal to a predetermined value, and transferring the first block pattern to the substrate.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Inventor: Ying-Wei Wang
  • Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device
    Publication number: 20100148271
    Abstract: The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift.
    Type: Application
    Filed: December 17, 2008
    Publication date: June 17, 2010
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Wu-Chun Kao, Ying-Hsuan Li, Ying-Wei Yen, Shu-Yen Chan