Abstract: An integrated circuit includes a first region including a first set of transistors that include a first set of active regions having a first threshold voltage, the first set of transistors in a first portion of a level shifter circuit, the first portion of the level shifter circuit being coupled to a first voltage supply. The integrated circuit further includes a second region adjacent to the first region. The second region includes a second set of transistors that include a second set of active regions having a second threshold voltage different from the first threshold voltage, and the second set of transistors being in a second portion of the level shifter circuit.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for a scenario of editing multimedia resources, a device and a storage medium. The method includes: in response to an editing instruction triggered for a target editing template, displaying an import page of a material segment to be edited corresponding to the target editing template, wherein a setting entry for the material segment to be edited and a prompt entry for the material segment to be edited are presented on the import page; in response to a trigger for the prompt entry, displaying an original material segment corresponding to the material segment to be edited; in response to a trigger operation for the setting entry, determining the material segment to be edited; and editing the material segment to be edited into a target multimedia resource in a target editing mode indicated by the target editing template.

Abstract: This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

Abstract: A Schmitt trigger circuit includes a first and second set of transistors, a first and second feedback transistor, and a first and second circuit. The first set of transistors is connected between a first voltage supply and an output node. The first voltage supply has a first voltage. The second set of transistors is connected between the output node and a second voltage supply. The second voltage supply has a second voltage. The first feedback transistor is connected to the output node, a first node and a second node. The second feedback transistor is connected to the output node, a third node and a fourth node. The first circuit is coupled to and configured to supply the second supply voltage to the second node. The second circuit is coupled to and configured to supply the first supply voltage to the fourth node.

Abstract: A sports bra shock absorption effect evaluation method includes: allowing a subject to wear a sports bra for an experimental test, adhering a total of 43 infrared reflective mark points on the body, and completing preparation; allowing the subject naturally to stand on a treadmill, and acquiring static coordinate data; starting the treadmill, acquiring dynamic coordinate data for 5 minutes in sports when a speed in sports reaches 6-12 km/h, and immediately asking a subjective perception of the subject after doing sports; converting the dynamic coordinate data into coordinate data in which a thoracic vertebra point is defined as an origin, and calculating a square root index S of displacement amplitude data in the left-right direction and the up-down direction; and numerically sorting the displacement amplitudes according to the square root index S, and corresponding to subjective perceptions one by one to obtain hierarchical definitions for an existing bra.

Abstract: This application provides a distributed power supply switching circuit for an eFuse memory. A distributed power supply domain switching module comprising an internal power supply VDDI, an internal power supply VQR, a first PMOS and a second PMOS. A source of the first PMOS is connected with the internal power supply VDDI, and a gate is connected with the internal power supply VQR. A source of the second PMOS is connected with the internal power supply VQR, and a gate is connected with the internal power supply VDDI. Bulks and drains of the first PMOS and the second PMOS are jointly connected with a node VLS. The distributed power supply domain switching module supplies power to a word line or bit line control module through the node VLS. The circuit of this application can avoiding the risk that the two power supplies are short-circuited.

Abstract: A fuse programming unit, comprising: two efuse units and a mode control tube. The first efuse unit includes: one end of the first fuse forms the first end, and the second end is connected to the drain end of the first MOS. The first MOS source terminal is grounded, and the first word line formed by the gate terminal. The second efuse unit includes: the first end of the second fuse forms the second wire end, and the second end is connected to the drain end of the second MOS. The second MOS source terminal is grounded, and the gate terminal forms the second line. The source end of the mode control transistor is connected to the line end of the second efuse unit, the drain end is connected to the source end of the first MOS, and the gate end forms the correction end.

Abstract: Disclosed in the embodiments of the present disclosure are a method and apparatus for multimedia resource editing scene, and a device and a storage medium. The method comprises: detecting whether a current time matches a specified time; in response to determining that the current time matches the specified time, presenting prompt information of a target editing template; where the target editing template is associated with a first multimedia resource; content of the first multimedia resource belongs to a content category associated with the specified time; the target editing template instructs to edit a to-be-edited multimedia material into a second multimedia resource in a target editing way; the target editing way is an editing way used by the first multimedia resource; and the prompt information is presentation information of the first multimedia resource.

Abstract: An integrated circuit includes an input circuit coupled to a first voltage supply, and configured to receive a first input signal, and to generate at least a second or a third input signal, and a level shifter circuit coupled to the input circuit and a second voltage supply, and configured to receive a first enable signal, the second or third input signal, and to generate a first signal responsive to the first enable signal, the second or third input signal. The input circuit includes a first set of transistors having a first threshold voltage. The first set of transistors includes a first set of active regions extending in a first direction. The level shifter circuit includes a second set of transistors having a second threshold voltage. The second set of transistors includes a second set of active regions extending in the first direction.

Abstract: A method of forming a semiconductor device includes forming a first row of transistors extending in a first direction and including dummy transistors and active transistors. The first row includes, in a sequence from a first end to a second end, at least a first dummy group, a first delay cell, a second delay cell, and a second dummy group. The first dummy group is formed of one or more dummy transistors. The second dummy group is formed of one or more dummy transistors. The first delay cell is formed of active transistors configured as a basic inverter and a float-resistant inverter. The second delay cell is formed of active transistors configured as at least one inverter. The first row is free of dummy transistors between the first delay cell and the second delay cell.

Abstract: The invention relate to video editing template search method, apparatus, electronic device and storage medium, wherein the method can acquire a search keyword input by a user, perform matching according to the search keyword to obtain a target music and a first template video; wherein the target music matches with the search keyword, the first template video is video edited by using a first editing template, and then present the user the first template video and the target music aggregately in a search result page in the form of card.

Abstract: A semiconductor device includes a substrate, an active region, an isolation structure, a first metal line, gate structure, source/drain region, a source/drain contact, and a second metal line. The active region protrudes from a top surface of the substrate. The isolation structure is over the substrate and laterally surrounds the active region. The first metal line is in the isolation structure. The gate structure is over the active region. The source/drain region is in the active region. The source/drain contact is over the active region and is electrically connected to the source/drain region. The second metal line is over the gate structure and the source/drain contact, in which the second metal line vertically overlaps the first metal line.

Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

Abstract: The present invention discloses an efuse unit and an application circuit, including a first fuse, a second fuse, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor. One end of the first fuse serves as a Q1 port of the efuse unit, and the other end is connected to a drain end of the third NMOS transistor and a drain end of the first NMOS transistor. One end of the second fuse serves as a Q2 port of the efuse unit, and the other end is connected to a source end of the third NMOS transistor and a drain end of the second NMOS transistor. Gate ends of the first NMOS transistor and the second NMOS transistor are short-circuited to form a WLC port of the efuse unit. The present invention can avoid reading operation failure caused by low programming resistance of the fuse.

Abstract: The present invention discloses an efuse unit, including a first fuse, a second fuse, a first NMOS, a second NMOS and a third NMOS. One end of the first fuse serves as a Q1 port, and the other end is connected to drain end of the third NMOS and the first NMOS. One end of the second fuse serves as a Q2 port and is short-circuited to a source end of the third NMOS, and the other end is connected to a drain end of the second NMOS. Agate end of the third NMOS serves as an RDWL port. A gate end of the first NMONS serves as a WLC port. A gate end of the second NMOS serves as a WL port. The present invention can improve the correctness of the reading operation, reduce the voltage required for the programming operation, reduce the programming current.

Abstract: A method and a system for identifying a glacial lake outburst debris flow (GLODF) are provided. The method is obtained based on considering induced influences of slopes of channels and particle sizes of source particles on the GLODF. The method not only compensates for deficiencies in identifying the GLODF, but also realizes determination of the GLODF, which provides data basis for disaster prevention and control layout such as monitoring and early warning on a glacial lake and assists preventing and managing disasters caused by the GLODF. Meanwhile, multiple parameters used in the method are easy and convenient to obtain, and the parameters can be directly used on site, which saves engineering cost, improves working efficiency, and has high practical and promotional value in environmental protection and disaster prevention and mitigation.

Abstract: An integrated circuit includes a control circuit and first to second voltage generation circuits. The control circuit is coupled between a first voltage terminal providing a first supply voltage and a first node coupled to a first capacitive unit. The first voltage generation circuit includes at least one first transistor that has a source terminal receiving a second supply voltage, a drain terminal coupled to a second node in contact with a second capacitive unit, and a gate terminal coupled to the first node. The second voltage generation circuit is coupled to the first voltage terminal and the first and second nodes. Firstly the control circuit turns on the at least one first transistor to adjust a voltage level of the second node to have the second supply voltage. The second voltage generation circuit adjusts a voltage level of the first node to have the first supply voltage.

Abstract: A three-dimensional orthogonal woven composite outlet guide vane and a manufacturing method are provided. Near-net-shaped manufacturing of the outlet guide vane is realized, and a vane profile-platform junction of the outlet guide vane is reinforced by designing a bifurcation of the preform. A basic structure of a three-dimensional orthogonal woven composite and a bifurcation of the vane profile-platform junction are used, so that the ultimate strength under tension, compression and bending of the outlet guide vane structure are significantly improved, and the weight of the outlet guide vane is reduced. Structural load bearing and force transmission functions of a strut are provided by the outlet guide vane while the functions of vane rectification, noise reduction and others are ensured. As a result, the weight and dimensions of an aeroengine, as well as structural complexity, are reduced by removing struts.

Abstract: A rapid detection tool for a coaxial relationship based on a photosensitive material and a detection method using the same are used to detect coaxiality of two through-holes in the same workpiece to be detected. An image processing unit and a control unit are mounted outside a light-shielding box. Light sources, cameras, sensors, and an air cylinder are mounted in the light-shielding box. A photosensitive plate coated with a photosensitive resin is placed between the two holes, and two sides are irradiated by the light sources. Coordinates of centers of circular patterns formed on the photosensitive plate are calculated so that a coaxial relationship between the two holes can be accurately obtained. An output rod of the air cylinder is controlled to extend outward to reject a workpiece to be detected not meeting requirements.

Abstract: A three-dimensional orthogonal woven composite outlet guide vane and a manufacturing method are provided. Near-net-shaped manufacturing of the outlet guide vane is realized, and a vane profile-platform junction of the outlet guide vane is reinforced by designing a bifurcation of the preform. A basic structure of a three-dimensional orthogonal woven composite and a bifurcation of the vane profile-platform junction are used, so that the ultimate strength under tension, compression and bending of the outlet guide vane structure are significantly improved, and the weight of the outlet guide vane is reduced. Structural load bearing and force transmission functions of a strut are provided by the outlet guide vane while the functions of vane rectification, noise reduction and others are ensured. As a result, the weight and dimensions of an aeroengine, as well as structural complexity, are reduced by removing struts.