Abstract: The invention relate to video editing template search method, apparatus, electronic device and storage medium, wherein the method can acquire a search keyword input by a user, perform matching according to the search keyword to obtain a target music and a first template video; wherein the target music matches with the search keyword, the first template video is video edited by using a first editing template, and then present the user the first template video and the target music aggregately in a search result page in the form of card.

Abstract: The present disclosure discloses an electronic fuse memory, which is added with an address switching module and an output mode selection module on the basis of conventional basic function modules, and is added with a dual-bit redundant mode enable signal DB as an enable signal for the dual-bit redundant working mode on the basis of original control signals, thus providing two working modes, i.e., a normal working mode and a dual-bit redundant working mode, for customers to select. In the normal working mode, all storage space can be used, and in the dual-bit redundant working mode, a redundant backup function can be achieved, thus achieving selectable input address length and selectable output result, ensuring the implementation of conventional and redundant operations. In the same electronic fuse memory, the capacity and the reliability can be balanced.

Abstract: This application provides a distributed power supply switching circuit for an eFuse memory. A distributed power supply domain switching module comprising an internal power supply VDDI, an internal power supply VQR, a first PMOS and a second PMOS. A source of the first PMOS is connected with the internal power supply VDDI, and a gate is connected with the internal power supply VQR. A source of the second PMOS is connected with the internal power supply VQR, and a gate is connected with the internal power supply VDDI. Bulks and drains of the first PMOS and the second PMOS are jointly connected with a node VLS. The distributed power supply domain switching module supplies power to a word line or bit line control module through the node VLS. The circuit of this application can avoiding the risk that the two power supplies are short-circuited.

Abstract: A distributed digital certificate implementation is described. Each of n participants generates a respective threshold private key share based on a distributed key generation protocol. Each of at least t+1 of the n participants generates a random value based on an offline-phase protocol. Each of the at least t+1 participants receives a certificate application, and generates a certificate share by signing application information in the certificate application based on an online-phase protocol, the threshold private key share, and the random value generated based on the offline-phase protocol. Any party aggregates at least t+1 signature shares into a total certificate after obtaining the at least t+1 certificate shares.

Abstract: The present application discloses an electronic fuse storage unit and a storage array thereof, the electronic fuse storage unit has a control transistor and a fuse that are formed in a same active area, an elongated-shape polycrystalline silicon fuse thereof is located at a side of an MOS control transistor and has an end shorted to an end of a drain-side heavily doped region of a nearest MOS control transistor, the area of the electronic fuse storage unit is significantly reduced and it is facilitated to directly perform a combination layout by forming storage unit pairs in a center-symmetric manner to form a storage unit array, and thus, a layout area of a storage array can be reduced to obviously increase the layout efficiency for composing the storage array by the electronic fuse storage unit.

Abstract: The present invention discloses an efuse unit, including a first fuse, a second fuse, a first NMOS, a second NMOS and a third NMOS. One end of the first fuse serves as a Q1 port, and the other end is connected to drain end of the third NMOS and the first NMOS. One end of the second fuse serves as a Q2 port and is short-circuited to a source end of the third NMOS, and the other end is connected to a drain end of the second NMOS. Agate end of the third NMOS serves as an RDWL port. A gate end of the first NMONS serves as a WLC port. A gate end of the second NMOS serves as a WL port. The present invention can improve the correctness of the reading operation, reduce the voltage required for the programming operation, reduce the programming current.

Abstract: The present disclosure provides an efuse memory, where an efuse cell structure includes a control transistor composed of a MOS transistor and a link structure. The MOS transistor is formed in a first active area. The link structure is formed in a second active area parallel to the first active area. The link structure includes first and second link connection areas, and an active area link located between the first and second link connection areas. The first link connection area is connected to a drain line of the MOS transistor. The second link connection area is connected to a bit line. The active area link includes on and off states.

Abstract: The present application discloses an efuse memory, and an efuse unit includes: a main fuse, a backup fuse, a main selection control transistor, and a backup selection control transistor. A first end of the main fuse and a first end of the backup fuse are connected. The main selection control transistor is connected between a second end of the main fuse and a source port. The backup selection control transistor is connected between a second end of the backup fuse and the source port. The second end of the backup fuse serves as a read port. In a programming operation, the main fuse and the backup fuse form a parallel structure. In a read operation, the backup fuse and the main fuse form a series structure. The present application also discloses a method for operating an efuse memory.

Abstract: The present invention discloses an efuse unit and an application circuit, including a first fuse, a second fuse, a first NMOS transistor, a second NMOS transistor and a third NMOS transistor. One end of the first fuse serves as a Q1 port of the efuse unit, and the other end is connected to a drain end of the third NMOS transistor and a drain end of the first NMOS transistor. One end of the second fuse serves as a Q2 port of the efuse unit, and the other end is connected to a source end of the third NMOS transistor and a drain end of the second NMOS transistor. Gate ends of the first NMOS transistor and the second NMOS transistor are short-circuited to form a WLC port of the efuse unit. The present invention can avoid reading operation failure caused by low programming resistance of the fuse.

Abstract: The present disclosure discloses an eFuse memory cell, which comprises a first selection transistor, a second selection transistor and a fuse-link, wherein a gate terminal of the first selection transistor is used as a BL port, a drain terminal of the first selection transistor is used as a Q port, and a source terminal of the first selection transistor is connected to a drain terminal of the second selection transistor as a SA port; a gate terminal of the second selection transistor is used as a WL port, and a source terminal of the second selection transistor is connected to one end of the fuse-link; the other end of the fuse-link is used as a gnd port. The present disclosure further discloses an eFuse memory array consisting of the eFuse memory cells.

Abstract: Systems and methods are taught for providing customers of a cloud computing service to control when updates affect the services provided to the customers. Because multiple customers share the cloud's infrastructure, each customer may have conflicting preferences for when an update and associated downtime occurs. Preventing and resolving conflicts between the preferences of multiple customers while providing them with input for scheduling a planned update may reduce the inconvenience posed by updates. Additionally, the schedule for the update may be transmitted to customers so that they can prepare for the downtime of services associated with the update.

Abstract: A display panel is provided. The display panel includes a substrate, and a plurality of anodes, a pixel definition layer, a light-emitting layer, and a cathode layer that are laminated on the substrate. By collecting the anodes spaced apart from each other in a first direction in a same first pixel opening, number of the first pixel openings in the display area can be reduced, and number of ink droplets that can be sprayed within a single first pixel opening can be increased, so that a risk of bridging between adjacent ones of pixel openings can be lowered.

Abstract: This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

Abstract: The present invention discloses an optical pulse design method for high-fidelity manipulation over ensemble qubits, so that fast and efficient two-color optical pulses that have high robustness against frequency detuning and a laser intensity fluctuation are constructed by using an inverse engineering method based on a Lewis-Riesenfeld invariant, and using a perturbation theory and a concept of a system error sensitivity. The pulses can be applied in an inhomogeneously broadened three-level system to create an arbitrary superposition state of ensemble qubits with a high fidelity. During action of the pulse, quantum manipulation has stronger robustness against instantaneous changes or spatial nonuniform distribution of a laser intensity. The robustness can increase a signal-to-noise ratio of a detected signal and reduce experimental difficulties.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for a scenario of editing multimedia resources, a device and a storage medium. The method includes: in response to an editing instruction triggered for a target editing template, displaying an import page of a material segment to be edited corresponding to the target editing template, wherein a setting entry for the material segment to be edited and a prompt entry for the material segment to be edited are presented on the import page; in response to a trigger for the prompt entry, displaying an original material segment corresponding to the material segment to be edited; in response to a trigger operation for the setting entry, determining the material segment to be edited; and editing the material segment to be edited into a target multimedia resource in a target editing mode indicated by the target editing template.

Abstract: This application discloses a one-time programmable memory cell, which includes one anti-fuse programmable transistor, one fuse, and two control transistors. One of a source end and a drain end of a first control transistor is connected to one of a source end and a drain end of the anti-fuse programmable transistor, and the other is connected to one of a source end and a drain end of a second control transistor and one end of the fuse. The other of the source end and the drain end of the second control transistor is connected to the ground. The one time programmable memory cell disclosed in this application can directly correct an error bit through reprogramming, can simplify circuit and layout design, requires a smaller layout area, and has higher reliability and safety.

Abstract: A sports bra shock absorption effect evaluation method includes: allowing a subject to wear a sports bra for an experimental test, adhering a total of 43 infrared reflective mark points on the body, and completing preparation; allowing the subject naturally to stand on a treadmill, and acquiring static coordinate data; starting the treadmill, acquiring dynamic coordinate data for 5 minutes in sports when a speed in sports reaches 6-12 km/h, and immediately asking a subjective perception of the subject after doing sports; converting the dynamic coordinate data into coordinate data in which a thoracic vertebra point is defined as an origin, and calculating a square root index S of displacement amplitude data in the left-right direction and the up-down direction; and numerically sorting the displacement amplitudes according to the square root index S, and corresponding to subjective perceptions one by one to obtain hierarchical definitions for an existing bra.

Abstract: This application provides a distributed power supply switching circuit for an eFuse memory. A distributed power supply domain switching module comprising an internal power supply VDDI, an internal power supply VQR, a first PMOS and a second PMOS. A source of the first PMOS is connected with the internal power supply VDDI, and a gate is connected with the internal power supply VQR. A source of the second PMOS is connected with the internal power supply VQR, and a gate is connected with the internal power supply VDDI. Bulks and drains of the first PMOS and the second PMOS are jointly connected with a node VLS. The distributed power supply domain switching module supplies power to a word line or bit line control module through the node VLS. The circuit of this application can avoiding the risk that the two power supplies are short-circuited.

Abstract: A fuse programming unit, comprising: two efuse units and a mode control tube. The first efuse unit includes: one end of the first fuse forms the first end, and the second end is connected to the drain end of the first MOS. The first MOS source terminal is grounded, and the first word line formed by the gate terminal. The second efuse unit includes: the first end of the second fuse forms the second wire end, and the second end is connected to the drain end of the second MOS. The second MOS source terminal is grounded, and the gate terminal forms the second line. The source end of the mode control transistor is connected to the line end of the second efuse unit, the drain end is connected to the source end of the first MOS, and the gate end forms the correction end.

Abstract: Disclosed in the embodiments of the present disclosure are a method and apparatus for multimedia resource editing scene, and a device and a storage medium. The method comprises: detecting whether a current time matches a specified time; in response to determining that the current time matches the specified time, presenting prompt information of a target editing template; where the target editing template is associated with a first multimedia resource; content of the first multimedia resource belongs to a content category associated with the specified time; the target editing template instructs to edit a to-be-edited multimedia material into a second multimedia resource in a target editing way; the target editing way is an editing way used by the first multimedia resource; and the prompt information is presentation information of the first multimedia resource.