Abstract: Examples of a data transmission method and apparatus in TEE systems are described. One example of the method includes: obtaining first data; obtaining a write offset address by reading a first address; obtaining a read offset address by reading a second address; determining whether the number of bytes in the first data is less than or equal to the number of writable bytes, where the number of writable bytes is determined based on the write offset address and the read offset address, and each address corresponds to one byte; when the number of bytes in the first data is less than or equal to the number of writable bytes, writing the first data into third addresses starting from the write offset address; and updating the write offset address in the first address.

Abstract: One or more implementations of the present specification provide a blockchain-based data authorization method and apparatus. The method can include receiving, by a blockchain node, an authentication transaction submitted by a privacy computing platform, where the authentication transaction queries whether a data user has obtained authorization of target data possessed by a data owner, and in response to determining that the data user has obtained authorization of the target data, executing, by the blockchain node, a smart contract invoked by the authentication transaction to provide an authorization token to the privacy computing platform that instructs the privacy computing platform to obtain the target data, and send a computational result of one or more predetermined computational operations based on the target data to the data user.

Abstract: Systems and methods are taught for providing customers of a cloud computing service to control when updates affect the services provided to the customers. Because multiple customers share the cloud's infrastructure, each customer may have conflicting preferences for when an update and associated downtime occurs. Preventing and resolving conflicts between the preferences of multiple customers while providing them with input for scheduling a planned update may reduce the inconvenience posed by updates. Additionally, the schedule for the update may be transmitted to customers so that they can prepare for the downtime of services associated with the update.

Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for configuring a field programmable gate array (FPGA) based trusted execution environment (TEE) for use in a blockchain network. One of the methods includes storing a device identifier (ID), a first random number, and a first encryption key in a field programmable gate array (FPGA) device; sending an encrypted bitstream to the FPGA device, wherein the encrypted bitstream can be decrypted by the first key into a decrypted bitstream comprising a second random number; receiving an encrypted message from the FPGA device; decrypting the encrypted message from the FPGA device using a third key to produce a decrypted message; in response to decrypting the encrypted message: determining a third random number in the decrypted message; encrypting keys using the third random number; and sending the keys to the FPGA device.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: In implementations of the present disclosure, a solution for managing a co-ownership database system is provided. In this solution, multiple members access the database system as the co-owner thereof. The database system comprises: an underlying database for storing data of multiple members of the database system, a rule set defining constraints on operations of the multiple members over the database system, and a blockchain storing a record of an operation history of the database system. The database system is co-owned by the multiple members. In response to receiving a data accessing request from one of members, the accessing request will be verified based on the rule set. Subsequently, the accessing request will be processed according to a result of the verification.

Abstract: A nanometer cutting depth high-speed single-point scratch test device includes a workbench, an air-bearing turntable, a test piece fixture, a test piece, a Z-direction feeding device, a nano positioning stage, a force sensor and a scratch tool. A micro convex structure with controllable length and height is machined in a position of the test piece to be scratched.

Abstract: Systems and methods are taught for providing customers of a cloud computing service to control when updates affect the services provided to the customers. Because multiple customers share the cloud's infrastructure, each customer may have conflicting preferences for when an update and associated downtime occurs. Preventing and resolving conflicts between the preferences of multiple customers while providing them with input for scheduling a planned update may reduce the inconvenience posed by updates. Additionally, the schedule for the update may be transmitted to customers so that they can prepare for the downtime of services associated with the update.

Abstract: Aspects of the technology described herein can facilitate computing on transient resources. An exemplary computing device may use a task scheduler to access information of a computational task and instability information of a transient resource. Moreover, the task scheduler can schedule the computational task to use the transient resource based at least in part on the rate of data size reduction of the computational task. Further, a checkpointing scheduler in the exemplary computing device can determine a checkpointing plan for the computational task based at least in part on a recomputation cost associated with the instability information of the transient resource. Resultantly, the overall utilization rate of computing resources is improved by effectively utilizing transient resources.

Abstract: Implementations of the specification include receiving, by a smart contract service provider including a trusted computation execution environment (TEE) from a client associated with a target blockchain network, a request for operating cross-chain data of one or more blockchain networks different from the target blockchain, wherein the smart contract service provider is off the target blockchain network; sending, by the smart contract service provider to a data visiting service provider, a request for the cross-chain data; receiving, by the smart contract service provider, the cross-chain data from the data visiting service provider; generating, by the TEE, a result using the cross-chain data; and returning, by the smart contract service provider, the result to the client.

Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.

Abstract: Aspects of the technology described herein can facilitate computing on transient resources. An exemplary computing device may use a task scheduler to access information of a computational task and instability information of a transient resource. Moreover, the task scheduler can schedule the computational task to use the transient resource based at least in part on the rate of data size reduction of the computational task. Further, a checkpointing scheduler in the exemplary computing device can determine a checkpointing plan for the computational task based at least in part on a recomputation cost associated with the instability information of the transient resource. Resultantly, the overall utilization rate of computing resources is improved by effectively utilizing transient resources.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying the plurality of lower conductive lines, a plurality of upper conductive lines overlying the insulating layer and the first conductive lines and extending in a second direction crossing the first direction, and a plurality of vias filled with a conductive material formed in the insulating layer. The plurality of upper conductive lines are arranged in the first direction with a first pitch. The plurality of vias includes first vias and second vias. At least one via of the first vias connects at least two lines of the plurality of lower conductive lines and one line of the plurality of upper conductive lines. An average width in the first direction of the first vias is different from an average width in the first direction of the second vias.

Abstract: A semiconductor device includes a first transistor having a first gate, a first source and a first drain, a second transistor having a second gate, a second source and a second drain, an isolation region separating the first transistor from the second transistor, and a local interconnect connecting at least one of the first source and the first drain to at least the second source and the second drain. The local interconnect is in contact with a surface of the at least one of the first source and the first drain, a surface of the at least the second source and the second drain and a surface of a part of the isolation region.

Abstract: A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.

Abstract: A semiconductor device comprises a first gate electrode disposed on a substrate, a first source/drain region, and a local interconnect connecting the first gate electrode and the first source/drain region. The local interconnect is disposed between the substrate and a first metal wiring layer in which a power supply line is disposed. The local interconnect has a key hole shape in a plan view, and has a head portion, a neck portion and a body portion connected to the head portion via the neck portion. The neck portion is disposed over the first gate electrode and the body portion is disposed over the first source/drain region.

Abstract: Aspects of the technology described herein can facilitate computing on transient resources. An exemplary computing device may use a task scheduler to access information of a computational task and instability information of a transient resource. Moreover, the task scheduler can schedule the computational task to use the transient resource based at least in part on the rate of data size reduction of the computational task. Further, a checkpointing scheduler in the exemplary computing device can determine a checkpointing plan for the computational task based at least in part on a recomputation cost associated with the instability information of the transient resource. Resultantly, the overall utilization rate of computing resources is improved by effectively utilizing transient resources.