Patents by Inventor Ying Yao
Ying Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250041416Abstract: A pharmaceutical combination comprising (i) a first component selected from an immune effector cell (e.g., a T cell and an NK cell) expressing a molecular switch-regulated CAR polypeptide, a nucleic acid molecule encoding the CAR polypeptide, a vector comprising the nucleic acid molecule, and any combination thereof; and (ii) a second component, which is an antibody that contains a P329G mutation and specifically binds to a B-cell maturation antigen (BCMA) protein. The present invention also relates to a kit comprising the pharmaceutical combination, and the use of the pharmaceutical combination in the treatment of BCMA-related diseases in a subject.Type: ApplicationFiled: December 7, 2022Publication date: February 6, 2025Applicant: INNOVENT CELLS PHARMACEUTICALS (SUZHOU) CO., LTD.Inventors: Wei XU, Huafeng WEI, Diana Binia DAROWSKI, Dan XU, Ying YAO, Bianka PRINZ, Nadthakarn BOLAND, James GEOGHEGAN
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Publication number: 20250015007Abstract: One aspect of the present disclosure pertains to an integrated (IC) structure. The IC structure includes a semiconductor substrate; an interconnect structure formed over the substrate; and a redistribution layer (RDL) structure formed over the interconnect structure. The RDL structure includes: a RDL pad portion having a pad via array with multiple vias landing on a first top metal line of the interconnect structure; a RDL signal routing portion having a signal routing via landing on a second top metal line of the interconnect structure; and a RDL top portion over the RDL pad portion and the RDL signal routing portion. The multiple vias of the pad via array include a block via and an adjacent sacrificial via, the block via having a block via width, the sacrificial via having a sacrificial via width, and the block via width is greater than the sacrificial via width.Type: ApplicationFiled: July 6, 2023Publication date: January 9, 2025Inventors: Yu-Chung Lai, Ying-Yao Lai, Chen-Chiu Huang, Hsiang-Ku Shen, Dian-Hau Chen, Kuo-An Liu, Tzu-Ting Liu
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Publication number: 20240379734Abstract: A semiconductor device includes a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: electrodes including one or more first electrodes and one or more second electrodes; and one or more insulating layers disposed between adjacent electrodes. The MIM capacitor is disposed in an interlayer dielectric (ILD) layer disposed over a substrate. The one or more first electrodes are connected to a side wall of a first via electrode disposed in the ILD layer, and the one or more second electrodes are connected to a side wall of a second via electrode disposed in the ILD layer. In one or more of the foregoing or following embodiments, the one or more insulating layers include a high-k dielectric material.Type: ApplicationFiled: July 24, 2024Publication date: November 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
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Publication number: 20240371920Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.Type: ApplicationFiled: July 20, 2024Publication date: November 7, 2024Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
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Publication number: 20240317640Abstract: A method for preparing a cover substrate is provided. The method includes the following steps: providing a substrate with an anti-reflection film formed thereon, wherein the anti-reflection film includes a first layer, and the first layer includes silicon oxide; and treating the first layer of the anti-reflection film with fluoride-based plasma to form a hydrophobic layer on the first layer, wherein a fluorine-containing radical in the fluoride-based plasma is reacted with the silicon oxide in the first layer to form the hydrophobic layer, wherein the fluoride-based plasma is decomposed from a fluoride-based compound by using microwave, and the fluoride-based compound includes NF3 or SF6.Type: ApplicationFiled: May 29, 2024Publication date: September 26, 2024Inventors: Ying-Yao TANG, Chin-Lung TING
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Patent number: 12098299Abstract: A chemical mechanical polishing slurry, including silicon dioxide particles, a nitrogen-containing heterocyclic compound having one or more carboxy group(s), and an ethoxylated butoxylated alky alcohol, and use of the chemical mechanical polishing slurry in the polishing silicon oxide, polysilicon, and silicon nitride. Polishing rate for silicon nitride using the polishing slurry is much higher than that for silicon oxide and polysilicon. The polishing slurry can be applied to chemical mechanical polishing in which silicon oxide/polysilicon is used as the stop layer, and can be used to control the amount of oxide and polysilicon removed from the substrate surface during polishing.Type: GrantFiled: December 18, 2019Date of Patent: September 24, 2024Assignee: ANJI MICROELECTRONICS (SHANGHAI) CO., LTD.Inventors: Wenting Zhou, Jianfen Jing, Ying Yao, Xinyuan Cai, Jian Ma, Heng Li
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Patent number: 12080753Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.Type: GrantFiled: June 19, 2023Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Chieh Hsiao, Hsiang-Ku Shen, Yuan-Yang Hsiao, Ying-Yao Lai, Dian-Hau Chen
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Publication number: 20240282628Abstract: A method of forming a semiconductor structure includes forming a seed layer on a substrate, forming a photoresist layer on the seed layer with a first opening wider than a second opening, performing an electroplating process with a first plating current to grow a bottom portion of a first metal line in the first opening and a bottom portion of a second metal line in the second opening, continuing the electroplating process with a second plating current that is larger than the first plating current to grow a top portion of the first metal line and a top portion of the second metal line, removing the photoresist layer to expose a portion of the seed layer, and removing the exposed portion of the seed layer.Type: ApplicationFiled: July 25, 2023Publication date: August 22, 2024Inventors: Dian-Hau CHEN, Chen-Chiu HUANG, Hsiang-Ku SHEN, ShuFang CHEN, Ying-Yao LAI, Wen-Ling CHANG, Chi-Feng LIN, Peng-Chung JANGJIAN, Jo-Lin LAN, Fang-I Chih
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Publication number: 20240274653Abstract: A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.Type: ApplicationFiled: April 15, 2024Publication date: August 15, 2024Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Tsung-Chieh Hsiao, Ying-Yao Lai, Dian-Hau Chen
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Patent number: 12013354Abstract: A pressure chamber has a chamber wall. The chamber wall includes a sensor integrated within the chamber wall, wherein the sensor integrated in the chamber wall comprises defects. A method of determining an effect of pressure on a material is further described. The method includes applying pressure to a material within a pressure chamber and to a pressure chamber wall of the pressure chamber, where the pressure chamber wall has defects. A signal from the defects is sensed while the material and the pressure chamber wall are under pressure. A property of the material is determined based on the sensed signal.Type: GrantFiled: December 19, 2019Date of Patent: June 18, 2024Assignee: The Regent of the University of CaliforniaInventors: Norman Ying Yao, Raymond Jeanloz, Thomas Mittiga, Prabudhya Bhattacharyya, Thomas J. Smart, Francisco Machado, Bryce Kobrin, Soonwon Choi, Joel Moore, Satcher Hsieh, Chong Zu
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Patent number: 11961880Abstract: A semiconductor device includes first and second metal-insulator-metal structures. The first metal-insulator-metal structure includes a first bottom conductor plate, a first portion of a first dielectric layer, a first middle conductor plate, a first portion of a second dielectric layer, and a first top conductor plate stacked up one over another. The second metal-insulator-metal structure includes a second bottom conductor plate, a second portion of the first dielectric layer, a second middle conductor plate, a second portion of the second dielectric layer, and a second top conductor plate stacked up one over another. In a cross-sectional view, the first bottom conductor plate is wider than the first middle conductor plate that is wider than the first top conductor plate, and the second bottom conductor plate is narrower than the second middle conductor plate that is narrower than the first top conductor plate.Type: GrantFiled: August 9, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Tsung-Chieh Hsiao, Ying-Yao Lai, Dian-Hau Chen
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Publication number: 20240062521Abstract: A method for object detection includes: extracting a plurality of identification features from a plurality of reference images that are related to a target object; selecting a plurality of selected identification features respectively from the identification features so as to obtain a first feature dataset, and storing the first feature dataset, a quantity of selected identification features being smaller than a quantity of the identification features; in response to receipt of a to-be-detected image, performing a feature extraction operation on the to-be-detected image to obtain a second feature dataset; performing a similarity determination operation with respect to the to-be-detected image based on the first feature dataset and the second feature dataset, and calculating a quantity of instances of the target object in the to-be-detected image.Type: ApplicationFiled: August 15, 2023Publication date: February 22, 2024Inventors: Cheng-Lung CHEN, Ying YAO, Xuan Loc NGUYEN, Ha Trung PHAM, Tafjira Nugraha BRILIAN
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Patent number: 11881386Abstract: A method for coating a curved substrate is disclosed, which includes: providing a coating device including: a chamber, a carrying platform, a sputtering mechanism, and a position-adjusting mechanism, wherein the carrying platform is disposed in the chamber and has a first surface, the sputtering mechanism is disposed in the chamber and is disposed corresponding to the carrying platform, and the position-adjusting mechanism is disposed in the chamber; providing a curved substrate, wherein the curved substrate is disposed on the first surface of the carrying platform and the curved substrate has a second surface; adjusting the sputtering mechanism to different positions by the position-adjusting mechanism; and sputtering a coating material to different parts of the second surface of the curved substrate by the sputtering mechanism at the different positions.Type: GrantFiled: July 8, 2021Date of Patent: January 23, 2024Assignee: INNOLUX CORPORATIONInventors: Ching-Feng Kuo, Chin Lung Ting, Ying-Yao Tang
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Patent number: 11842303Abstract: Disclosed is a method for processing an irradiation forecast. The method includes: acquiring irradiation forecast data corresponding to a target time period; calling a stacked generalization model including a first-layer generalizer and a second-layer generalizer; determining, using the first-layer generalizer, intermediate forecast data based on the irradiation forecast data corresponding to the target time period; and determining, using the second-layer generalizer, an output forecast value corresponding to the target time period based on the intermediate forecast data. In a technical solution according to an embodiment of the present disclosure, a method for processing an irradiation forecast is achieved.Type: GrantFiled: November 13, 2020Date of Patent: December 12, 2023Assignees: ENVISION DIGITAL INTERNATIONAL PTE. LTD., SHANGHAI ENVISION DIGITAL CO., LTD.Inventors: Zibo Dong, Ying Yao, Yangyang Zhao, Hui Yang, Qingsheng Zhao
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Publication number: 20230352394Abstract: A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than ?0.3 GPa.Type: ApplicationFiled: April 28, 2022Publication date: November 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Te CHU, Yuan-Yang HSIAO, Chih-Pin CHIU, Ying-Yao LAI, Mao-Nan WANG, Chen-Chiu HUANG, Dian-Hau CHEN
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Publication number: 20230335517Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.Type: ApplicationFiled: June 23, 2023Publication date: October 19, 2023Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
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Publication number: 20230335578Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.Type: ApplicationFiled: June 19, 2023Publication date: October 19, 2023Inventors: Tsung-Chieh HSIAO, Hsiang-Ku SHEN, Yuan-Yang HSIAO, Ying-Yao LAI, Dian-Hau CHEN
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Patent number: 11782523Abstract: Disclosed are a method for controlling an Internet of Things (IoT) device, and a terminal device. The method is applied to a terminal device and includes: acquiring parameter information of a triggered key of a mouse; determining a target device and target operation information acting on the target device based on the parameter information; and sending device information of the target device and the target operation information to a server.Type: GrantFiled: August 30, 2021Date of Patent: October 10, 2023Assignee: BEIJING XIAOMI MOBILE SOFTWARE CO., LTD.Inventors: Yaming Li, Jianxing Zhao, Ying Yao, Haitao Yuan, Kangxi Tan
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Publication number: 20230317631Abstract: Methods for forming a back-end-of-line (BEOL) passive device structure are provided. A method according to the present disclosure includes depositing a first conductor layer over a substrate, patterning the first conductor layer to form a patterned first conductor layer, depositing a first insulation layer over the patterned first conductor layer, depositing a second conductor layer over the first insulation layer, patterning the second conductor layer to form a patterned second conductor layer, depositing a second insulation layer over the patterned second conductor layer, depositing a third conductor layer over the second insulation layer, and patterning the third conductor layer to form a patterned third conductor layer. The patterning of the first conductor layer includes removing a right-angle edge of the first conductor layer.Type: ApplicationFiled: April 1, 2022Publication date: October 5, 2023Inventors: Yuan-Yang Hsiao, Tsung-Chieh Hsiao, Wen-Chiung Tu, Ying-Yao Lai, Chen-Te Chu, Mao-Nan Wang, Chen-Chiu Huang, Dian-Hau Chen
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Patent number: 11746257Abstract: The present invention discloses a chemical mechanical polishing slurry, the chemical mechanical polishing slurry comprises silica abrasive particles, a corrosion inhibitor, a complexing agent, an oxidizer, and at least one kind of polyacrylic acid anionic surfactant. The polishing slurry of the present invention can decrease the removal rate of tantalum while increasing the removal rate of copper, and reduce copper dishing and dielectric erosion after polish.Type: GrantFiled: December 26, 2018Date of Patent: September 5, 2023Assignee: Anji Microelectronics (Shanghai) Co., Ltd.Inventors: Jian Ma, Jianfen Jing, Junya Yang, Kai Song, Xinyuan Cai, Guohao Wang, Ying Yao, Pengcheng Bian