Patents by Inventor Ying-Ying Wang
Ying-Ying Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170007542Abstract: The present invention generally relates to reducing the mucoadhesive properties of a particle. In some embodiments, the particle is coated with and/or associated with a (poly(ethylene glycol))-(poly(propylene oxide))-(poly(ethylene glycol)) triblock copolymer. Methods for preparing inventive particles using a poly(ethylene glycol)-vitamin E conjugate as a surfactant are also provided. In some embodiments, methods are provided comprising administering to a subject a composition of particles of the present invention. Such particles with reduced mucoadhesive properties are useful in delivering agents to mucosal tissues such as oral, ophthalmic, gastrointestinal, nasal, respiratory, and genital mucosal tissues.Type: ApplicationFiled: March 9, 2016Publication date: January 12, 2017Inventors: Samuel K. Lai, Ming Yang, Ying-Ying Wang, Olcay Mert, Laura Ensign, Justin Hanes, Jie Fu
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Publication number: 20160240443Abstract: An overlay measurement and correction method and device is provided. In an embodiment the measurement device takes measurements of a first semiconductor wafer and uses the measurements in a plurality of correction techniques to generate an overlay correction model. The plurality of correction techniques include a first order correction, a first intra-field high order parameter correction and a first inter-field high order parameter correction. The model is used to adjust the exposure parameters for the exposure of the next semiconductor wafer. The process is repeated on each semiconductor wafer for a run-to-run analysis.Type: ApplicationFiled: July 20, 2015Publication date: August 18, 2016Inventors: Yung-Yao Lee, Heng-Hsin Liu, Yi-Ping Hsieh, Ying Ying Wang
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Publication number: 20160033878Abstract: One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: Yung-Yao Lee, Ying-Ying Wang
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Publication number: 20160025650Abstract: The present disclosure provides an overlay metrology method, an overlay control method and an overlay control system. The overlay metrology method includes capturing a current layer image of a current overlay mark on a current layer with a current focal length and capturing a previous layer image of a previous overlay mark on a previous layer with a previous focal length. Then, the overlay metrology method further includes combining the current layer image with the previous layer image to form an overlay mark image and determining an overlay error between the current overlay mark and the previous overlay mark based on the overlay mark image.Type: ApplicationFiled: July 22, 2014Publication date: January 28, 2016Inventors: Yung-Yao LEE, Ying-Ying WANG, Shang-Wern CHANG, Heng-Hsin LIU
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Patent number: 9176396Abstract: One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.Type: GrantFiled: February 27, 2013Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Yao Lee, Ying-Ying Wang
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Publication number: 20150302127Abstract: Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design.Type: ApplicationFiled: June 29, 2015Publication date: October 22, 2015Inventors: Po-Chang Huang, Ying Ying Wang, Shellin Liu, Kuan-Chi Chen
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Patent number: 9164398Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.Type: GrantFiled: April 14, 2014Date of Patent: October 20, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Yao Lee, Ying-Ying Wang, Yi-Ping Hsieh, Heng-Hsin Liu
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Publication number: 20150284451Abstract: The presently-disclosed subject matter relates to antibodies, compositions, and methods for inhibiting and treating pathogen infection and providing contraception. In particular, the presently-disclosed subject matter relates to inhibiting and treating pathogen infection and providing contraception in a subject using compositions and antibodies capable of trapping pathogens or sperm in mucus, thereby inhibiting transport of pathogens or sperm across mucus secretions. The subject matter further relates to methods for monitoring the effectiveness of vaccines by detecting antibodies capable of trapping pathogens in mucus.Type: ApplicationFiled: October 29, 2013Publication date: October 8, 2015Inventors: Samuel Lai, Ying-Ying Wang, Arthi Kannan, Kennetta Nunn, Durai Babu Subramani, Richard Cone
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Patent number: 9104831Abstract: Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design.Type: GrantFiled: August 23, 2013Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Chang Huang, Ying Ying Wang, Shellin Liu, Kuan-Chi Chen
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Publication number: 20150116686Abstract: An edge-dominant alignment method for use in an exposure scanner system is provided. The method includes the steps of: providing a wafer having a plurality of shot areas, wherein each shot area has a plurality of alignment marks; determining a first outer zone of the wafer, wherein the first outer zone includes a first portion of the shot areas along a first outer edge of the wafer; determining a scan path according to the shot areas of the first outer zone; and performing an aligning process to each shot area of the first outer zone according to the scan path and an alignment mark of each shot area of the first outer zone.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Yao LEE, Ying-Ying WANG, Yi-Ping HSIEH, Heng-Hsin LIU
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Publication number: 20150058817Abstract: Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design.Type: ApplicationFiled: August 23, 2013Publication date: February 26, 2015Inventors: Po-Chang Huang, Ying Ying Wang, Shellin Liu, Kuan-Chi Chen
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Publication number: 20150042994Abstract: Among other things, one or more systems and techniques for scanner alignment sampling are provided. A set of scan region pairs are defined along a periphery of a sampling area associated with a semiconductor wafer. Alignment marks are formed within scan regions of the set of scan region pairs, but are not formed within other regions of the sampling area. In this way, scan region pairs are scanned to determine alignment factors for respective scan region pairs. An alignment for the sampling area, such as layers or masks used to form patterns onto such layers, is determined based upon alignment factors determined for the scan region pairs.Type: ApplicationFiled: August 12, 2013Publication date: February 12, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Lee Yung-Yao, Ying Ying Wang, Yi-Ping Hsieh
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Publication number: 20150016943Abstract: Some embodiments of the present disclosure relate to a method of alignment which includes defining a plurality of fields on the face of a wafer, and organizing the plurality of fields into an orthogonal field structure and two or more continuous field structures. A first number of alignment structure positions are measured within each field of the two or more continuous field structures, and a second number of alignment structure positions are measured within each field of the orthogonal field structure, the second number being greater than the first number. The feature or layer is then aligned to the previously formed feature or layer based upon the measured alignment structure positions of the two or more continuous field structures and the orthogonal field structure.Type: ApplicationFiled: July 12, 2013Publication date: January 15, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ping Hsieh, Yung-Yao Lee, Ying Ying Wang, Shin-Rung Lu
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Patent number: 8860941Abstract: One embodiment relates to a method for semiconductor workpiece processing. In this method, a baseline tool induced shift (TIS) is measured by performing a baseline number of TIS measurements on a first semiconductor workpiece. After the baseline TIS has been determined, the method determines a subsequent TIS based on a subsequent number of TIS measurements taken on a first subsequent semiconductor workpiece. The subsequent number of TIS measurements is less than the baseline number of TIS measurements.Type: GrantFiled: April 27, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Yao Lee, Ying Ying Wang, Heng-Hsin Liu, Heng-Jen Lee
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Patent number: 8822019Abstract: A coated article includes a substrate, a first layer deposited on the substrate, a second layer deposited on the first layer and a third layer deposited on the second layer. The first layer substantially consists of one material selected from the group consisting of Al layer, Al alloy layer, Zn layer or Zn alloy layer. The first layer is white. The second layer substantially includes metal M?, O and N, wherein M? is Al or Zn. The third layer is an aluminum oxide layer or a silicon oxide layer. The third layer has an anti-fingerprint property.Type: GrantFiled: September 21, 2011Date of Patent: September 2, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Wen-Rong Chen, Cheng-Shi Chen, Ying-Ying Wang, Zhi-Jie Hu, Cong Li
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Publication number: 20140240706Abstract: A process of measuring overlay metrologies of wafers, the wafer having a plurality of patterned layers. The process begins with retrieving historical overlay metrologies from a database, and real overlay metrologies of a first group of the wafers are measured. On the other hand, virtual overlay metrologies of a second group of the wafers are calculated with the retrieved historical overly metrologies. The real overlay metrologies of the first group of the wafers and the virtual overlay metrologies of the second group of the wafers are stored to the database as the historical overlay metrologies.Type: ApplicationFiled: April 14, 2014Publication date: August 28, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yung-Yao LEE, Ying-Ying WANG, Yi-Ping HSIEH, Heng-Hsin LIU
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Publication number: 20140240703Abstract: One embodiment relates to a method for overlay sampling. The method provides a number of fields over a semiconductor wafer surface. An inner subgroup of the number of fields includes fields in a central region of the wafer surface. An outer subgroup of the number of fields includes neighboring fields near a circumferential edge of the wafer surface. The method measures a first number of overlay conditions at a corresponding first number of overlay structures within a field of the inner subgroup. The method also measures a second number of overlay conditions at a corresponding second number of overlay structures within a field of the outer subgroup. The second number is greater than the first number. Based on the measured first number of overlay conditions and the measured second number of overlay conditions, the method determines an alignment condition for two or more layers on the semiconductor wafer surface.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yung-Yao Lee, Ying-Ying Wang
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Patent number: 8741444Abstract: A process for surface treating iron-based alloy includes providing a substrate made of iron-based alloy. A chromium layer is then formed on the substrate by vacuum sputtering. A silicon oxide layer, an alumina layer, and a boron nitride layer are formed in that order by vacuum evaporation.Type: GrantFiled: August 25, 2011Date of Patent: June 3, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Hsin-Pei Chang, Wen-Rong Chen, Huann-Wu Chiang, Cheng-Shi Chen, Ying-Ying Wang
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Patent number: 8703368Abstract: A process for use in lithography, such as photolithography for patterning a semiconductor wafer, is disclosed. The process includes receiving an incoming semiconductor wafer having various features and layers formed thereon. A unit-induced overlay (uniiOVL) correction is received and a deformation measurement is performed on the incoming semiconductor wafer in an overlay module. A deformation-induced overlay (defiOVL) correction is generated from the deformation measurement results by employing a predetermined algorithm on the deformation measurement results. The defiOVL and uniiOVL corrections are fed-forward to an exposure module and an exposure process is performed on the incoming semiconductor wafer.Type: GrantFiled: July 16, 2012Date of Patent: April 22, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Lee, Ying Ying Wang, Heng-Hsin Liu, Chin-Hsiang Lin
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Patent number: 8637148Abstract: A coated article includes a bonding layer, an iridium layer, a chromium oxynitride layer and a chromium nitride layer formed on a substrate in that order. The substrate is made of die steel.Type: GrantFiled: June 29, 2011Date of Patent: January 28, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd, Hon Hai Precision Industry Co., Ltd.Inventors: Hsin-Pei Chang, Wen-Rong Chen, Huann-Wu Chiang, Cheng-Shi Chen, Ying-Ying Wang