Abstract: The present disclosure is related to a thin film transistor. The thin film transistor may include an active layer; a gate insulating layer on the active layer; and a gate and a plurality of metal films on the gate insulating layer. The plurality of metal films may be spaced apart from the gate, and insulated from the gate and the active layer.

Abstract: A thin film transistor (TFT), a manufacturing method, an array substrate, a display panel, and a device is disclosed. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.

Abstract: A metal oxide film and a manufacturing method thereof, a thin film transistor and an array substrate are provided. The manufacturing method of the metal oxide film includes: forming a metal oxide film on a base substrate; and supplying a negative ion to the metal oxide film for a preset time period by performing a anodization method, to convert a portion of metal ions in the metal oxide film into a metal oxide.

Abstract: A display panel includes a substrate; a conductive layer disposed on the substrate; a gate insulating layer disposed on the conductive layer; a gate layer disposed on the gate insulating layer, wherein the gate layer has a thickness larger than a thickness of the conductive layer; a groove extending toward the substrate and punching through the gate layer, orthographic projections of the groove and the conductive layer on the substrate overlapping, and gate layers separated on two sides of the groove being connected to the conductive layer; an interlayer dielectric layer disposed on a side of the gate layer away from the substrate and covering the conductive layer and filling the groove; and an auxiliary electrode layer disposed on the interlayer dielectric layer, wherein the orthographic projections of the auxiliary electrode layer and the gate layer on substrate do not overlap, and the orthographic projections of the auxiliary electrode layer and the groove on the substrate overlap.

Abstract: The present disclosure provides an OLED display panel and a method for detecting the OLED display panel, and a display device. The OLED display panel includes a base substrate including a display area and a non-display area surrounding the display area and having a first region adjacent to the display area. The display area includes a drive signal line and a power supply voltage signal line both extending from the display area to the first region. The drive signal line includes, in the first region, a first section of wiring at an anode layer, the power supply voltage signal line includes, in the first region, a second section of wiring at a gate metal layer, and parts of the drive signal line and the power supply voltage signal line in the display area are located at a source-drain metal layer.

Abstract: Embodiments of the present disclosure provide a method and a device for detecting a threshold voltage drift of a transistor in a pixel circuit, which are used for detecting the threshold voltage drift of the transistor to be detected in the pixel circuit. The transistor to be detected is at least one of the driving transistor and the detection transistor. The detection method comprises: inputting, during an inputting stage, a first turning-on voltage to the second scanning terminal, so as to turn on the detection transistor, enabling writing a first voltage into the second node through the detection signal terminal; inputting, during a detection stage, a first turning-off voltage to the second scanning terminal, so as to turn off the detection transistor, thereby detecting an actual voltage at the second node; and determining a state of the threshold voltage drift of the transistor to be detected according to the actual voltage and the first voltage.

Abstract: Provided is a thin film transistor, including: a conductive light shielding layer; a metal oxide layer arranged on the light shielding layer; a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer arranged in sequence on the metal oxide layer, the interlayer insulating layer and the buffer layer comprising a first via hole and a second via hole for exposing the active layer, and a third via hole for exposing the metal oxide layer, in which a portion of the metal oxide layer exposed through the third via hole is a conductive portion, and other portions are insulative; and a source electrode and a drain electrode arranged on the interlayer insulating layer, in which the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole and connected to the conductive portion through the third via hole.

Abstract: The present disclosure provides a pixel defining layer and a preparation material thereof, and a display substrate and a preparation method thereof, and relates to the field of display technologies. The preparation material of the pixel defining layer comprises the following components in mass percentages: 5%-30% of a lyophobic film-forming polymer, 0.5%-1% of lyophilic magnetic nanoparticles, 0.5%-2% of a photoinitiator, 0.1%-1% of a reactive monomer, 0.1%-1% of an additive and the balance of a solvent.

Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.

Abstract: The present disclosure provides a transistor and a manufacturing method thereof, a display substrate and a display device. The transistor includes: a base structure; an active layer on the base structure; and a gate electrode, a source electrode and a drain electrode that are all located on a side of the active layer distal to the base structure. The active layer includes a first region corresponding to an orthographic projection of the gate electrode on the base structure and a second region outside the orthographic projection. A surface of the base structure in contact with the active layer in the first region is not in the same plane as a surface of the base structure in contact with the active layer in the second region. The active layer in the first region has substantially the same thickness as a thickness of the active layer in the second region.

Abstract: The present disclosure provides a positive photoresist composition including a major adhesive material and a photosensitizer, wherein the photoresist composition further includes a photoisomerizable compound which would be converted into an ionic structure with an increased degree of molecular polarity after ultraviolet irradiation. The formation of the ionic structure with increased polarity of the molecule reduces the adhesion between the positive photoresist and the organic film layer, facilitates stripping after formation of the via, and improves the product rate of pass. Further, the present disclosure provides a via-forming method using the positive resist composition, a display substrate including the via formed by the via-forming method, and a display device including the display substrate.

Abstract: A display substrate, a method for manufacturing the display substrate, and a display device are provided. The display substrate includes a display area and a fanout area at the periphery of the display area. The fanout area includes a data line layer, a first power line layer, and at least two insulation layers between the data line layer and the first power line layer. In a direction perpendicular to a base substrate of the display substrate, the first power line layer overlaps the data line layer. At least one of the at least two insulation layers includes a portion which insulates the first power line layer and the data line layer from each other.

Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.

Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.

Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.

Abstract: A sterilization structure, a sterilization board, and a display device are disclosed. The sterilization structure includes an active layer, wherein, one surface of the active layer has an exposed region, and a material of the active layer includes a laser-induced graphene material.

Abstract: The present disclosure provides a method for determining a width-to-length ratio of a channel region of a thin film transistor (TFT). The method includes: S1, setting an initial width-to-length ratio of the channel region; S2, manufacturing a TFT by using a mask plate according to the initial width-to-length ratio; S3, testing the TFT manufactured according to the initial width-to-length ratio; S4, determining whether or not the test result satisfies a predetermined condition, performing S5 if the test result satisfies the predetermined condition, and performing S6 if the test result does not satisfy the predetermined condition; S5, determining the initial width-to-length ratio as the width-to-length ratio of the channel region of the TFT; S6, changing the value of the initial width-to-length ratio, adjusting a position of the mask plate according to the changed initial width-to-length ratio, and performing S2 to S4 again.

Abstract: A metal oxide film and a manufacturing method thereof, a thin film transistor and an array substrate are provided. The manufacturing method of the metal oxide film includes: forming a metal oxide film on a base substrate; and suppling a negative ion to the metal oxide film for a preset time period by performing a anodization method, to convert a portion of metal ions in the metal oxide film into a metal oxide.

Abstract: A method of manufacturing an array substrate assembly, an array substrate assembly manufactured by the method, and a display panel including the array substrate assembly are disclosed. The method includes: providing a substrate, the substrate having a first region as a preset semiconductor-removed region, and a second region as a remaining region; forming, in the first region of the substrate, a semiconductor removing layer corrodible by a corrosive solution; and forming a semiconductor layer on the substrate formed with the semiconductor removing layer, so that the semiconductor layer covers the semiconductor removing layer.

Abstract: A thin film transistor and a method of fabricating the same, an array substrate and a method of fabricating the same, and a display device are provided, the method of fabricating a thin film transistor includes: forming an active layer on a base substrate; forming a metal layer on the active layer; and processing the metal layer to form a source electrode, a drain electrode, and a metal oxide layer, the metal oxide layer covering the source electrode, the drain electrode, and the active layer, the source electrode and the drain electrode being spaced apart and insulated from each other by the metal oxide layer.