Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include performing a sense operation on a particular memory cell of a first string of series-connected memory cells selectively connected to a first data line, applying a first voltage level to the access line for a second memory cell of the first string, applying a second voltage level higher than the first voltage level to the access line for the particular memory cell, applying a third voltage level to the first data line concurrently with applying the first voltage level and concurrently with applying the second voltage level, and applying a fourth voltage level higher than the third voltage level to a second data line selectively connected to a second string of series-connected memory cells concurrently with applying the third voltage level to the first data line.

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.

Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. A discharge period is set based on a position of the selected word line in a stack or block of memory cells. The discharge period is longer when the selected word line is in the lower tier than in the upper tier. Additionally, the discharge period is longer when the selected word line is at a top of the lower tier than at a bottom of the lower tier. Other options to increase the discharge include increasing a ramp up rate and a peak level of the word line voltages during the discharge period as a function of the position of the selected word line.

Abstract: Techniques for reducing neighbor word line interference (NWI) of memory cells which are formed in a two-tier stack having a lower tier and an upper tier separated by an interface. In one approach, an upward word line programming order is used for a top portion of the top tier, and a downward word line programming order is used for a bottom portion of the top tier and for the bottom tier. Additionally, for memory cells which receive NWI from both adjacent word lines, options include programming fewer bits per cell, performing multi-pass programming and/or use lower verify voltages. Options also include increasing a control gate length of the memory cells and increasing a height of a dielectric region adjacent to the memory cells.

Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. A discharge period is set based on a position of the selected word line in a stack or block of memory cells. The discharge period is longer when the selected word line is in the lower tier than in the upper tier. Additionally, the discharge period is longer when the selected word line is at a top of the lower tier than at a bottom of the lower tier. Other options to increase the discharge include increasing a ramp up rate and a peak level of the word line voltages during the discharge period as a function of the position of the selected word line.

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.

Abstract: An apparatus having an erase controller configured to perform a two-sided gate-induced drain leakage (GIDL) erase of non-volatile memory cells is disclosed. The erase controller is configured to apply a first voltage pulse having a first value for a voltage pulse attribute to the first end of a first pathway. The erase controller is configured to apply a second voltage pulse having a second value for the voltage pulse attribute to the first end of a second pathway. The first value and the second value are configured to compensate for different impedances such that a first erase voltage at a first select transistor is substantially symmetric with a second erase voltage at a second select transistor.

Abstract: An apparatus comprising an impedance compensation circuit is disclosed. The impedance compensation circuit compensates for impedance differences between a first pathway connected to a first transistor and a second pathway connected to a second transistor. However, rather than making a compensation based on a signal (e.g., voltage) applied to either the first or the second pathway, a compensation is made based on the signals (e.g., voltage pulses) applied to third and fourth pathways connected to the transistors.

Abstract: Techniques for reducing read disturb of memory cells in a two-tier stack having a lower tier and an upper tier separated by an interface. In a read operation, the channels of NAND strings are discharged before reading the selected memory cells. The discharge involves ramping up the word line voltages and grounding the ends of the NAND strings. To increase the discharge, a ramp up rate may be greater for the selected word line and for dummy memory cells adjacent to the interface, compared to the ramp up rate for the unselected word lines. In an option, the greater ramp up rate is also used for the word lines between the selected word line and the interface. In another option, the greater ramp up rate is used for the word lines in the same tier as the selected word line.

Abstract: Methods and systems for improving the reliability of stored data in the presence of cross-temperature variation are described. To reduce the number of data errors caused by cross-temperature variation, two or more sensing passes may be performed corresponding with two or more different sensing times. The amount of shifting in the memory cell threshold voltages may be determined on a per-bit basis or on a cell-by-cell basis based on the sensing operations performed during the two or more sensing passes. The stored data states may be assigned based on the amount of shifting in the memory cell threshold voltages during the two or more sensing passes and the type of cross-temperature variation present (e.g., whether the memory cells were programmed at a temperature above 65 degrees Celsius and read back at a temperature below 25 degrees Celsius).

Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart among one another by line trenches and a two-dimensional array of memory stack structures and a two-dimensional array of dielectric pillar structures located in the line trenches. Each line trench is filled with laterally alternating sequence of memory stack structures and dielectric pillar structures. Each memory stack structure contains a vertical semiconductor channel, a pair of blocking dielectrics contacting outer sidewalls of the vertical semiconductor channel, a pair of charge storage layers contacting outer sidewalls of the pair of blocking dielectrics, and a pair of tunneling dielectrics contacting outer sidewalls of the pair of charge storage layers.

Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.

Abstract: A non-volatile memory system is provided that includes a plurality of NAND strings of non-volatile storage elements, each non-volatile storage element including a control gate, a tunneling layer, a floating gate, and a blocking layer including a ferroelectric material. The tunneling layer is disposed between the control gate and the floating gate, and the floating gate is disposed between the tunneling layer and the blocking layer.

Abstract: Apparatuses and techniques are provided for accurately reading memory cells by compensating for lateral charge diffusion between adjacent memory cells. A selected memory cell is read with a compensation which is based on classifying the threshold voltages of adjacent memory cells into bins. In one aspect, the compensation is based on the level of the current control gate voltage of the selected word line. In another aspect, the classifying of the threshold voltages of the adjacent memory cells can be a function of temperature. In another aspect, a memory cell can be read with compensation after a previous read operation without compensation results in an uncorrectable error. In another aspect, the classifying uses more bins for a selected edge word line.