Patents by Inventor Yingda Dong

Yingda Dong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230044240
    Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
    Type: Application
    Filed: October 20, 2022
    Publication date: February 9, 2023
    Inventors: Ching-Huang Lu, Vinh Q. Diep, Zhengyi Zhang, Yingda Dong
  • Publication number: 20230031362
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.
    Type: Application
    Filed: July 28, 2021
    Publication date: February 2, 2023
    Inventors: Haitao Liu, Kamal M. Karda, Albert Fayrushin, Yingda Dong
  • Publication number: 20230022858
    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
    Type: Application
    Filed: October 5, 2022
    Publication date: January 26, 2023
    Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
  • Patent number: 11508449
    Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 22, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Ching-Huang Lu, Vinh Q. Diep, Zhengyi Zhang, Yingda Dong
  • Patent number: 11488677
    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: November 1, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
  • Publication number: 20220336028
    Abstract: A memory device includes a memory array of memory cells. A page buffer is to apply, to a bit line, a first voltage or a second voltage that is higher than the first voltage during a program verify operation. Control logic operatively coupled with the page buffer is to perform operations including: causing a plurality of memory cells to be programmed with a first program pulse; measuring a threshold voltage for the memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the memory cells as having a faster quick charge loss than that of a second subset of the memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells.
    Type: Application
    Filed: April 19, 2021
    Publication date: October 20, 2022
    Inventors: Violante Moschiano, Yingda Dong
  • Publication number: 20220215890
    Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 11380709
    Abstract: A memory element is provided that includes a portion of a bit line plug, a portion of a source line plug, a portion of a word line, a portion of a vertical semiconductor pillar disposed between the bit line plug, the source line plug and adjacent the word line, and a gate oxide including a ferroelectric material disposed between the vertical semiconductor pillar and the word line.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 5, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Yingda Dong, James Kai, Christopher J. Petti
  • Publication number: 20220199175
    Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.
    Type: Application
    Filed: March 2, 2021
    Publication date: June 23, 2022
    Inventors: Ching-Huang Lu, Vinh Q. Diep, Zhengyi Zhang, Yingda Dong
  • Publication number: 20220189555
    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 16, 2022
    Inventors: Vinh Q. Diep, Ching-Huang Lu, Yingda Dong
  • Publication number: 20220189570
    Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.
    Type: Application
    Filed: December 10, 2020
    Publication date: June 16, 2022
    Inventors: Kalyan Chakravarthy Kavalipurapu, George Matamis, Yingda Dong, Chang H. Siau
  • Publication number: 20220189565
    Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.
    Type: Application
    Filed: March 8, 2022
    Publication date: June 16, 2022
    Inventors: Hong-Yan Chen, Yingda Dong
  • Publication number: 20220149068
    Abstract: An electronic device comprises a stack of alternating dielectric materials and conductive materials, a pillar region extending vertically through the stack, an oxide material within the pillar region and laterally adjacent to the dielectric materials and the conductive materials of the stack, and a storage node laterally adjacent to the oxide material and within the pillar region. A charge confinement region of the storage node is in horizontal alignment with the conductive materials of the stack. A height of the charge confinement region in a vertical direction is less than a height of a respective, laterally adjacent conductive material of the stack in the vertical direction. Related methods and systems are also disclosed.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Inventors: Yifen Liu, Yan Song, Albert Fayrushin, Naiming Liu, Yingda Dong, George Matamis
  • Publication number: 20220130475
    Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.
    Type: Application
    Filed: January 5, 2022
    Publication date: April 28, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jun Xu, Yingda Dong
  • Patent number: 11282582
    Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data block of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong-Yan Chen, Yingda Dong
  • Publication number: 20220051721
    Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 11238946
    Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jun Xu, Yingda Dong
  • Publication number: 20210391016
    Abstract: A processing device in a memory system initiates a program operation on the memory device, the program operation comprising a seeding phase. The processing device further causes a seeding voltage to be applied to a string of memory cells in a data block of the memory device during the seeding phase of the program operation and causes a positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase. Each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Hong-Yan Chen, Yingda Dong
  • Publication number: 20210391024
    Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.
    Type: Application
    Filed: June 12, 2020
    Publication date: December 16, 2021
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 11183245
    Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causes a first positive pre-boosting voltage to be applied to a first plurality of word lines of a data block of the memory array during the pre-boosting phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hong-Yan Chen, Yingda Dong