Abstract: A pixel driving circuit and a driving method thereof, and a display device. The pixel driving circuit includes a light-emitting driving circuit, a light-emitting component and a gate-source voltage adjustment circuit. A control end, a first end and a second end of the light-emitting driving circuit are electrically connected with a first node, a second node and the light-emitting component respectively; the gate-source voltage adjustment circuit is electrically connected with at least one of the first node and the second node, the gate-source voltage adjustment circuit is also electrically connected with an adjustment voltage terminal, and the gate-source voltage adjustment circuit is configured to adjust at least one of a voltage of the first node and a voltage of the second node, so as to increase a modulus value of a voltage difference between the control end and the first end of the light-emitting driving circuit.

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Abstract: There is provided in the present disclosure a shift register unit, comprising: an input circuit, whose first terminal is connected to a power supply terminal, second terminal is connected to an input terminal, and third terminal is connected to a pull-up node, the input circuit being configured to input a power supply signal input by the power supply terminal to the pull-up node under the control of an input signal; a pull-up control circuit, whose first terminal is connected to a first clock signal terminal, and second terminal is connected to the pull-up node, the pull-up control circuit being configured to control a potential of the pull-up node according to a first clock signal input by the first clock signal terminal; a pull-up circuit, whose first terminal is connected to a first signal terminal, second terminal is connected to an output terminal, third terminal is connected to the pull-up node.

Abstract: An array substrate, a display panel, a display device and a driving method. The array substrate includes: a plurality of first pixel units arranged in an array in a first region; a first gate driving circuit a second gate driving circuit; a plurality of first gate lines connected with the first gate driving circuit; and a plurality of second gate lines connected with the second gate driving circuit. A first portion of the plurality of first pixel units is connected with the plurality of first gate lines, and each first pixel unit in the first portion is connected with one of the plurality of first gate lines; and a second portion of the plurality of first pixel units is connected with the plurality of second gate lines, and each first pixel unit in the second portion is connected with one of the plurality of second gate lines.

Abstract: A display device and a light source are provided. The display device includes a display panel and a first photonic crystal layer arranged at a light-emitting side of the display panel. The first photonic crystal layer is configured to enable incident light to exit along a Z direction, the Z direction being a thickness direction of the first photonic crystal layer.

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

Abstract: A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.

Abstract: A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

Abstract: A pixel driving circuit and a driving method thereof, and a display device. The pixel driving circuit includes a light-emitting driving circuit, a light-emitting component and a gate-source voltage adjustment circuit. A control end, a first end and a second end of the light-emitting driving circuit are electrically connected with a first node, a second node and the light-emitting component respectively; the gate-source voltage adjustment circuit is electrically connected with at least one of the first node and the second node, the gate-source voltage adjustment circuit is also electrically connected with an adjustment voltage terminal, and the gate-source voltage adjustment circuit is configured to adjust at least one of a voltage of the first node and a voltage of the second node, so as to increase a modulus value of a voltage difference between the control end and the first end of the light-emitting driving circuit.

Abstract: A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.

Abstract: A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

Abstract: An in-cell touch screen and a display device, a touch electrode pattern is disposed on a side of the opposite substrate (100) facing the array substrate (200); a data line (210) and a gate line (220) are disposed on a side of the array substrate (200) facing the opposite substrate (100), the data line (210) and the gate line (220) intercross and are mutually insulated from each other; and a common electrode layer (230) is disposed on a layer where the gate line and the data line are located; and an orthographic projection of the common electrode layer (230) on the array substrate (200) covers orthographic projections of the gate line (220) and the data line (210). The in-cell touch screen can avoid various display problems and touch problems caused by insufficient time periods in a time division driving manner.

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

Abstract: An in-cell touch screen and a display device, a touch electrode pattern is disposed on a side of the opposite substrate (100) facing the array substrate (200); a data line (210) and a gate line (220) are disposed on a side of the array substrate (200) facing the opposite substrate (100), the data line (210) and the gate line (220) intercross and are mutually insulated from each other; and a common electrode layer (230) is disposed on a layer where the gate line and the data line are located; and an orthographic projection of the common electrode layer (230) on the array substrate (200) covers orthographic projections of the gate line (220) and the data line (210). The in-cell touch screen can avoid various display problems and touch problems caused by insufficient time periods in a time division driving manner.

Abstract: The present invention relates to a highly reliable nonvolatile memory and a manufacturing method thereof. The nonvolatile memory comprises top electrodes, bottom electrodes and a resistive material layer disposed therebetween, wherein the top electrodes are positioned on top in the memory; the bottom electrodes are positioned on a substrate; metal oxide for forming the resistive material layer is doped with metal; and a metal oxygen storage layer is further disposed between the top electrodes and the resistive material layer. The manufacturing method adopts a method in which a doping method and a double-layer forming method are combined, so that the highly reliable and highly uniform resistive random access memory can be fabricated and accordingly the performance of the memory can be increased.

Abstract: A protective plate and a preparation method thereof, a display panel and a display device. The protective plate comprises a translucent substrate, wherein a white shading frame, for covering a circuit layer, is provided in a periphery of the translucent substrate. In this way, it is possible to make a non-display region of the display panel be white.