Patents by Inventor Yinglong Huang
Yinglong Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9214629Abstract: A resistive memory having a leakage inhibiting characteristic and a method for fabricating the same, which can suppress a sneak current in a large scaled crossing array of a RRAM. A memory cell forming the resistive memory comprises a lower electrode, a first semiconductor-type oxide layer, a resistive material layer, a second semiconductor-type oxide layer and an upper electrode which are sequentially stacked. Each of the semiconductor-type oxide layers may be a semiconductor-type metal oxide or a semiconductor-type non-metal oxide. The sneak current may be effectively reduced by means of a Schottky barrier formed between the semiconductor-type oxide layer and the metal electrode, the fabrication process is easy to be implemented, and a high device integration degree can be achieved.Type: GrantFiled: April 26, 2013Date of Patent: December 15, 2015Assignee: Peking UniversityInventors: Ru Huang, Yinglong Huang, Yimao Cai, Yangyuan Wang, Muxi Yu
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Publication number: 20150349253Abstract: The present invention relates to a highly reliable nonvolatile memory and a manufacturing method thereof. The nonvolatile memory comprises top electrodes, bottom electrodes and a resistive material layer disposed therebetween, wherein the top electrodes are positioned on top in the memory; the bottom electrodes are positioned on a substrate; metal oxide for forming the resistive material layer is doped with metal; and a metal oxygen storage layer is further disposed between the top electrodes and the resistive material layer. The manufacturing method adopts a method in which a doping method and a double-layer forming method are combined, so that the highly reliable and highly uniform resistive random access memory can be fabricated and accordingly the performance of the memory can be increased.Type: ApplicationFiled: September 30, 2013Publication date: December 3, 2015Inventors: Ru Huang, Muxi Yu, Yimao Cai, Wenliang Bai, Yinglong Huang
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Patent number: 9142768Abstract: Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.Type: GrantFiled: May 2, 2012Date of Patent: September 22, 2015Assignee: Peking UniversityInventors: Yimao Cai, Jun Mao, Ru Huang, Shenghu Tan, Yinglong Huang, Yue Pan
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Publication number: 20150021539Abstract: Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.Type: ApplicationFiled: May 2, 2012Publication date: January 22, 2015Inventors: Yimao Cai, Jun Mao, Ru Huang, Shenghu Tan, Yinglong Huang, Yue Pan
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Patent number: 8936975Abstract: A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage.Type: GrantFiled: February 11, 2014Date of Patent: January 20, 2015Assignees: Beijing Boe Optoelectronics Technology Co., Ltd., Boe Technology Group Co., Ltd.Inventors: Yinglong Huang, Zheng Wang
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Patent number: 8937691Abstract: According to the embodiments of the invention, a TFT-LCD array substrate, a manufacturing method thereof and a TFT-LCD are provided. The TFT-LCD array substrate comprises: a gate line; a gate line test line; a gate line test terminal; a gate line drive circuit connected to the gate line; and a test TFT. A gate electrode and a drain electrode of the test TFT are connected to the gate line test line, a source electrode of the test TFT is connected to the gate line, and the gate line test terminal is connected to the gate line test line.Type: GrantFiled: October 21, 2011Date of Patent: January 20, 2015Assignee: Boe Technology Group Co., Ltd.Inventors: Yang Sun, Yinglong Huang, Jing Lv
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Publication number: 20140306173Abstract: A resistive memory having a leakage inhibiting characteristic and a method for fabricating the same, which can suppress a sneak current in a large scaled crossing array of a RRAM. A memory cell forming the resistive memory comprises a lower electrode, a first semiconductor-type oxide layer, a resistive material layer, a second semiconductor-type oxide layer and an upper electrode which are sequentially stacked. Each of the semiconductor-type oxide layers may be a semiconductor-type metal oxide or a semiconductor-type non-metal oxide. The sneak current may be effectively reduced by means of a Schottky barrier formed between the semiconductor-type oxide layer and the metal electrode, the fabrication process is easy to be implemented, and a high device integration degree can be achieved.Type: ApplicationFiled: April 26, 2013Publication date: October 16, 2014Inventors: Ru Huang, Yinglong Huang, Yimao Cai, Yangyuan Wang, Muxi Yu
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Publication number: 20140162415Abstract: A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage.Type: ApplicationFiled: February 11, 2014Publication date: June 12, 2014Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Yinglong HUANG, Zheng WANG
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Patent number: 8681089Abstract: A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage.Type: GrantFiled: March 4, 2010Date of Patent: March 25, 2014Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Yinglong Huang, Zheng Wang
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Patent number: 8633465Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.Type: GrantFiled: February 8, 2012Date of Patent: January 21, 2014Assignee: Peking UniversityInventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
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Publication number: 20130217199Abstract: The present invention discloses a method for fabricating a resistive memory, including: fabricating a bottom electrode over a substrate; partially oxidizing a metal of the bottom electrode through dry-oxygen oxidation or wet-oxygen oxidation to form a metal oxide with a thickness of 3 nm to 50 nm as a resistive material layer; finally fabricating a top electrode over the resistive material layer. The present invention omits a step of depositing a resistive material layer in a conventional method, so as to greatly reduce the process complexity. Meanwhile, a self alignment between the resistive material layer and the bottom electrode can be realized. A full isolation between devices may be ensured so as to obviate the parasite effects occurred in the conventional process methods. Meanwhile, the actual area and designed area of the device are ensured to be consistent.Type: ApplicationFiled: April 16, 2012Publication date: August 22, 2013Applicant: PEKING UNIVERSITYInventors: Ru Huang, Shenghu Tan, Lijie Zhang, Yue Pan, Yinglong Huang, Gengyu Yang, Yu Tang, Jun Mao, Yimao Cai
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Patent number: 8513639Abstract: The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.Type: GrantFiled: April 12, 2011Date of Patent: August 20, 2013Assignee: Peking UniversityInventors: Yimao Cai, Ru Huang, Yangyuan Wang, Yinglong Huang
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Patent number: 8405788Abstract: A thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a plurality of gate lines, a plurality of data lines and a plurality of common electrode lines. A plurality of pixel regions are formed by crossing of the plurality of gate lines and the plurality of data lines, a pixel electrode and a thin film transistor are provided for each pixel region, and one common electrode line is common to two vertically adjacent pixel regions.Type: GrantFiled: March 5, 2010Date of Patent: March 26, 2013Assignee: Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Yinglong Huang, Heecheol Kim
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Publication number: 20130069031Abstract: The present invention discloses a multilevel resistive memory having large storage capacity, which belongs to a field of a fabrication technology of a resistive memory. The resistive memory includes an top electrode and a bottom electrode, and a combination of a plurality of switching layers and defective layers interposed between the top electrode and the bottom electrode, wherein, the top electrode and the bottom electrode are respectively contacted with a switching layer (a film such as Ta2O5, TiO2, HfO2), and the defective layers (metal film such as Ti, Au, Ag) are interposed between the switching layers. By using the present invention, a storage capacity of a resistive memory can be increased.Type: ApplicationFiled: February 8, 2012Publication date: March 21, 2013Applicant: PEKING UNIVERSITY NO. 5 YIHEYUAN ROAD HAIDIAN DISTRICTInventors: Ru Huang, Gengyu Yang, Yimao Cai, Yu Tang, Lijie Zhang, Yue Pan, Shenghu Tan, Yinglong Huang
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Publication number: 20120289004Abstract: The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device.Type: ApplicationFiled: October 14, 2011Publication date: November 15, 2012Applicant: PEKING UNIVERSITYInventors: Ru Huang, Zhiqiang Li, Yue Guo, Xia An, Quanxin Yun, Yinglong Huang, Xing Zhang
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Publication number: 20120243085Abstract: Embodiments of the disclosed technology provide a three dimensional (3D) display device, comprising: an optical lens group, display panels, and a display plane, wherein the display panels comprises a first display panel and a second display panel for emitting image light with different polarization states, and wherein the optical lens group is used to refract polarized light emitted from the first and second display panels onto the display plane, so that the image light emitted from the first and second display panels forms images on the display plane. In addition, a 3D display system comprising the above 3D display device is also provided.Type: ApplicationFiled: March 20, 2012Publication date: September 27, 2012Applicant: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yang SUN, Yinglong HUANG, Jing LV
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Publication number: 20120241712Abstract: The present invention discloses a resistive-switching memory and the fabrication method thereof. The resistive-switching memory comprises a substrate, a top electrode, a bottom electrode, and a resistive-switching material interposed between the top and bottom electrodes, wherein the central portion of the bottom electrode protrudes upwards to form a peak shape, and the top electrode is in a plate shape. The peak structure of the bottom electrode reduces power consumption of the device. The fabrication method thereof comprises forming peak structures on the surface of the substrate by means of corrosion, and then growing bottom electrodes thereon to form bottom electrodes having peak shapes, and depositing resistive-switching material and top electrodes. The entire fabrication process is simple, and high integration degree of the device can be achieved.Type: ApplicationFiled: April 12, 2011Publication date: September 27, 2012Inventors: Yimao Cai, Ru Huang, Yangyuan Wang, Yinglong Huang
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Publication number: 20120099043Abstract: According to the embodiments of the invention, a TFT-LCD array substrate, a manufacturing method thereof and a TFT-LCD are provided. The TFT-LCD array substrate comprises: a gate line; a gate line test line; a gate line test terminal; a gate line drive circuit connected to the gate line; and a test TFT. A gate electrode and a drain electrode of the test TFT are connected to the gate line test line, a source electrode of the test TFT is connected to the gate line, and the gate line test terminal is connected to the gate line test line.Type: ApplicationFiled: October 21, 2011Publication date: April 26, 2012Applicant: BOE Technology Group Co., Ltd.Inventors: Yang SUN, Yinglong HUANG, Jing LV
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Publication number: 20100225860Abstract: A thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a plurality of gate lines, a plurality of data lines and a plurality of common electrode lines. A plurality of pixel regions are formed by crossing of the plurality of gate lines and the plurality of data lines, a pixel electrode and a thin film transistor are provided for each pixel region, and one common electrode line is common to two vertically adjacent pixel regions.Type: ApplicationFiled: March 5, 2010Publication date: September 9, 2010Applicant: Beijing BOE Optoelectronics Technoloy Co., Ltd.Inventors: Yinglong HUANG, Heecheol KIM
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Publication number: 20100225609Abstract: A touch display comprising a first substrate formed with a common electrode; a second substrate formed with a gate line and a data line, wherein a first thin film transistor and a pixel electrode is provided in a pixel region defined by the gate line and the data line and the pixel region and the common electrode form a liquid crystal capacitor; a touch element provided in the pixel region in the second substrate and used to sense a touch voltage reflecting the change of the liquid crystal capacitance at a touch point; and a touch processing device connected with the touch element and used to obtaining a position coordinates of the touch point according to the touch voltage.Type: ApplicationFiled: March 4, 2010Publication date: September 9, 2010Applicant: Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Yinglong HUANG, Zheng WANG