Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: In some implementations, a method of wireless communications between a wireless communications network and wireless user equipment includes receiving, using a primary Time Division Duplex (TDD) configuration, data on a primary component carrier in a first frequency band. Using a secondary TDD configuration, data on a secondary component carrier is received in a second frequency band different from the first frequency band. A Hybrid Automatic Repeat Request (HARQ) for data received on the secondary component carrier is transmitted using a supplemental TDD configuration. A transmission or retransmission on the secondary component carrier uses a supplemental TDD configuration as well. The supplemental TDD configuration is different from the secondary TDD configuration. Furthermore, an uplink supplemental configuration may be different from a downlink supplemental configuration.

Abstract: A vibration suppression method and system of a rolling mill roller assembly based on a vibration damping device are provided. The vibration suppression method includes: obtaining a first amplitude-frequency relationship during a vibration process of a rolling mill roller assembly vibration suppression system; based on the first amplitude-frequency relationship, determining two time domain relationships and two second amplitude-frequency relationships by a simulation analysis; based on the two time domain and relationships two second amplitude-frequency relationships, adjusting parameters of the vibration damping device until a vibration displacement of the rolling mill roller assembly vibration suppression system is less than or equal to a vibration displacement threshold. And provides a new solution for the stability control of the rolling mill, and ensures the reliability and stability of the vibration suppression of the rolling mill.

Abstract: A vibration suppression method and system of a rolling mill roller assembly based on a vibration damping device are provided. The vibration suppression method includes: obtaining a first amplitude-frequency relationship during a vibration process of a rolling mill roller assembly vibration suppression system; based on the first amplitude-frequency relationship, determining two time domain relationships and two second amplitude-frequency relationships by a simulation analysis; based on the two time domain relationships and two second amplitude-frequency relationships, adjusting parameters of the vibration damping device until a vibration displacement of the rolling mill roller assembly vibration suppression system is less than or equal to a vibration displacement threshold. And provides a new solution for the stability control of the rolling mill, and ensures the reliability and stability of the vibration suppression of the rolling mill.

Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.

Abstract: A method of forming a microelectronic device comprises forming a preliminary stack structure over a source structure. The preliminary stack structure comprises a vertically alternating sequence of insulative material and sacrificial material arranged in preliminary tiers. The method comprises forming a staircase structure having steps comprising edges of at least some of the preliminary tiers of the preliminary stack structure, forming implant regions within exposed portions of the sacrificial material at the steps of the staircase structure, forming openings extending through the preliminary stack structure to the source structure and within a horizontal area of the staircase structure, replacing portions of the sacrificial material with conductive structures, forming strapping structures comprising conductive material, at locations vacated by the implant regions, laterally adjacent to the conductive structures at the steps of the staircase structure, and forming conductive contacts within the openings.

Abstract: Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers comprise a first silicon oxide. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a flight of stairs. The stairs individually comprise a tread comprising conductive material of one of the conductive tiers. Individual of the treads comprise a second silicon oxide directly above the conductive material of the one conductive tier. The second silicon oxide comprises one or more of boron and phosphorus at a total concentration that is greater than a total concentration of one or more of boron and phosphorus, if any, that is in the first silicon oxide that is directly below the second silicon oxide.

Abstract: In some implementations, a method of wireless communications between a wireless communications network and wireless user equipment includes receiving, using a primary Time Division Duplex (TDD) configuration, data on a primary component carrier in a first frequency band. Using a secondary TDD configuration, data on a secondary component carrier is received in a second frequency band different from the first frequency band. A Hybrid Automatic Repeat Request (HARQ) for data received on the secondary component carrier is transmitted using a supplemental TDD configuration. A transmission or retransmission on the secondary component carrier uses a supplemental TDD configuration as well. The supplemental TDD configuration is different from the secondary TDD configuration. Furthermore, an uplink supplemental configuration may be different from a downlink supplemental configuration.

Abstract: Methods, systems, and devices for staircase landing pads via rivets are described. A memory device may include a staircase region with a stack of materials that includes a set of word lines, where the set of word lines progressively decrease in length to form a staircase structure. The staircase region may additionally include a rivet that couples a first word line from the set of word lines with a conductive pillar. Additionally, the conductive pillar may traverse the stack perpendicularly to the set of word lines and may couple the first word line with supporting circuitry. In some cases, a first thickness of the first word line adjacent to the conductive pillar may be greater than a second thickness of other word lines adjacent to the conductive pillar. The staircase region may additionally include an oxide material that isolates the conductive pillar from the other word lines.

Abstract: Methods, systems, and devices for NAND staircase landing pads conversion are described. A memory device may include one or more lateral word line contacts that may couple a word line with a conductive pillar that traverses a stack of materials of the memory device. The use of the lateral word line contact may allow for a conductive pillar to be coupled with a target word line without requiring an end of the conductive pillar to be placed directly on the word line. Additionally, the memory architecture described herein may allow for the target word line to be coupled with CMOS circuitry via a first conductive pillar without the use of a second conductive pillar, as the first conductive pillar may traverse the stack of materials and be coupled with the CMOS circuitry. Therefore, total quantity of conductive pillars may be reduced, and the risk of manufacturing errors may be lowered.

Abstract: In some implementations, a method of wireless communications between a wireless communications network and wireless user equipment includes receiving, using a primary Time Division Duplex (TDD) configuration, data on a primary component carrier in a first frequency band. Using a secondary TDD configuration, data on a secondary component carrier is received in a second frequency band different from the first frequency band. A Hybrid Automatic Repeat Request (HARQ) for data received on the secondary component carrier is transmitted using a supplemental TDD configuration. A transmission or retransmission on the secondary component carrier uses a supplemental TDD configuration as well. The supplemental TDD configuration is different from the secondary TDD configuration. Furthermore, an uplink supplemental configuration may be different from a downlink supplemental configuration.

Abstract: A method used in forming a conductive via of integrated circuitry comprises forming a lining laterally over sidewalls of an elevationally-elongated opening. The lining comprises elemental-form silicon. The elemental-form silicon of an uppermost portion of the lining is ion implanted in the elevationally-elongated opening. The ion-implanted elemental-form silicon of the uppermost portion of the lining is etched selectively relative to the elemental-form silicon of a lower portion of the lining below the uppermost portion that was not subjected to said ion implanting. The elemental-form silicon of the lower portion of the lining is reacted with a metal halide to form elemental-form metal in a lower portion of the elevationally-elongated opening that is the metal from the metal halide. Conductive material in the elevationally-elongated opening is formed atop and directly against the elemental-form metal. Other embodiments, including structure independent of method, are disclosed.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, a liner structure, conductive contact structures, and barrier structures. The stack structure comprises vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually comprises one of the conductive structures and one of the insulative structures. The staircase structure has steps comprising edges of at least some of the tiers of the stack structure. The first liner material is on the steps of the staircase structure, and the liner structure on the first liner material. The conductive contact structures extend through the first liner material and the liner structure and to the conductive structures of the stack structure. The barrier structures are between the conductive contact structures and the liner structure vertically span substantially the same tiers of the stack structure as the liner structure.

Abstract: Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. Conductive masses are formed that comprise at least one of conductively-doped semiconductive material or conductive metal material. Individual of the conductive masses are atop and directly electrically coupled to individual of the lower channel-material strings. Upper channel-material strings of select-gate transistors are formed directly above the stack. Individual of the upper channel-material strings are directly above and directly electrically coupled to individual of the conductive masses. Other embodiments, including structure, are disclosed.

Abstract: A microelectronic device comprises a stack structure, a staircase structure, a first liner material, an etch stop structure, and conductive contact structures. The stack structure includes conductive structures and insulative structures arranged in tiers. The stack structure includes sidewalls horizontally bounding the staircase structure. The staircase structure has steps includes edges of tiers of the stack structure. The first liner material is on the steps and the sidewalls and includes horizontally extending portions on the steps and vertically extending portions on the sidewalls. The etch stop structure is on the horizontally extending portions of the first liner material, the vertically extending portions of the first liner material being free of the etch stop structure. The conductive contact structures extend through the etch stop structure and the first liner material and to the conductive structures.

Abstract: A microelectronic device includes a stack structure comprising blocks separated from one another by dielectric slot structures and each including a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. At least one of the blocks comprising a stadium structure comprising opposing staircase structures each having steps comprising edges of the tiers; and a filled trench vertically overlying and within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench includes a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions and at least one dielectric structure doped with one or more of carbon and boron on the dielectric liner material, the at least one dielectric structure horizontally overlapping the steps of the stadium structure.

Abstract: Some embodiments include an integrated assembly having a first structure containing semiconductor material, and having a second structure contacting the first structure. The first structure has a composition along an interface with the second structure. The composition includes additive to a concentration within a range of from about 1018 atoms/cm3 to about 1021 atoms/cm3. The additive includes one or more of carbon, oxygen, nitrogen and sulfur. Some embodiments include methods of forming integrated assemblies.

Abstract: The present application relates to an all-optical detector and detection system, a response time test system, and a manufacturing method. The all-optical detector comprises a micro-nanofiber and an optical resonant cavity. The micro-nanofiber comprises transition regions and a uniform region. The uniform region is connected to the transition regions. The optical resonant cavity is provided in the uniform region. The optical resonant cavity is made of a semiconductor material. The all-optical detector provided in the present application detects light by means of the change of a resonance peak, achieves all-optical detection, and has a high signal-to-noise ratio.