Patents by Inventor Yiqun Bai
Yiqun Bai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112971Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Yiqun Bai, Dingying Xu, Srinivas Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ziyin Lin, Bai Nie, Haobo Chen, Kyle Arrington, Bohan Shan
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Patent number: 11749585Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.Type: GrantFiled: February 28, 2020Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Yiqun Bai, Vipul Mehta, John Decker, Ziyin Lin
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Patent number: 11688634Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.Type: GrantFiled: July 30, 2019Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Vipul Mehta, Yiqun Bai, Ziyin Lin, John Decker, Yan Li
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Publication number: 20230089928Abstract: Semiconductor devices having hollow filler materials are disclosed. A disclosed example semiconductor device includes at least one of a substrate or an interposer, interconnects extending through the at least one of the substrate or the interposer, and a composite material integral with or covering at least a portion of the semiconductor device, the composite material including a polymer matrix with a hollow filler material having voids therein.Type: ApplicationFiled: September 22, 2021Publication date: March 23, 2023Inventors: Ziyin Lin, Yiqun Bai, Hongxia Feng, Dingying Xu, Jieying Kong, Srinivas Pietambaram
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Patent number: 11574851Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 27, 2019Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Patent number: 11562940Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 8, 2019Date of Patent: January 24, 2023Assignee: Intel CorporationInventors: Elizabeth Nofen, James C. Matayabas, Jr., Yawei Liang, Yiqun Bai
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Patent number: 11545407Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: GrantFiled: January 10, 2019Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, Jr.
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Publication number: 20220196941Abstract: Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, where the package substrate comprises a recessed edge. In an embodiment, a compute die is on the package substrate, and an optics die on the package substrate and overhanging the recessed edge of the package substrate. In an embodiment, an integrated heat spreader (IHS) is over the compute die and the optics die.Type: ApplicationFiled: December 17, 2020Publication date: June 23, 2022Inventors: Asako TODA, Chia-Pin CHIU, Xiaoqian LI, Yiqun BAI
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Publication number: 20220196937Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to hydrophobic features to block or slow the spread of epoxy. These hydrophobic features are placed either on a die surface or on a substrate surface to control epoxy spread between the die in the substrate to prevent formation of fillets. Packages with these hydrophobic features may include a substrate, a die with a first side and a second side opposite the first side, the second side of the die physically coupled with a surface of the substrate, and a hydrophobic feature coupled with the second side of the die or the surface of the substrate to reduce a flow of epoxy on the substrate or die. In embodiments, these hydrophobic features may include a chemical barrier or a laser ablated area on the substrate or die. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Bassam ZIADEH, Jingyi HUANG, Yiqun BAI, Ziyin LIN, Vipul MEHTA, Joseph VAN NAUSDLE
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Publication number: 20220102242Abstract: Techniques and mechanisms for facilitating heat conductivity in a packaged device with a dummy die. In an embodiment, a packaged device comprises a substrate and one or more IC die coupled to a surface thereof. A dummy die, adjacent to an IC die and coupled to a region of the substrate, comprises a polymer resin and a filler. A package mold structure of the packaged device adjoins respective sides of the IC die and the dummy die, and adjoins the surface of the substrate. In another embodiment, a first CTE of the dummy die is less than a second CTE of the package mold structure, and a first thermal conductivity of the dummy die is greater than a second thermal conductivity of the package mold structure.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Mitul Modi, Joseph Van Nausdle, Omkar Karhade, Edvin Cetegen, Nicholas Haehn, Vaibhav Agrawal, Digvijay Raorane, Dingying Xu, Ziyin Lin, Yiqun Bai
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Publication number: 20210272878Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a mold material layer abutting electronic substrate and substantially surrounding the at least one integrated circuit, and at least one structure within the mold material layer, wherein the at least one structure comprises a material having a modulus of greater than about 20 gigapascals and a thermal conductivity of greater than about 10 watts per meter-Kelvin.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Yiqun Bai, Vipul Mehta, John Decker, Ziyin Lin
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Publication number: 20210035859Abstract: Embodiments disclosed herein include composite dies and methods of forming such composite dies. In an embodiment, a composite die comprises a base substrate, a first die over the base substrate, and a second die over the base substrate and adjacent to the first die. In an embodiment an underfill layer is between the first die and the base substrate, between the second die and the base substrate, and between the first die and the second die. In an embodiment, a trench into the underfill layer is between the first die and the second die. In an embodiment the composite die further comprises, a mold layer over the first die and the second die, wherein the mold layer fills the trench.Type: ApplicationFiled: July 30, 2019Publication date: February 4, 2021Inventors: Vipul MEHTA, Yiqun BAI, Ziyin LIN, John DECKER, Yan LI
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Publication number: 20200286806Abstract: An apparatus is provided which comprises: a die comprising an integrated circuit, a first material layer comprising a first metal, the first material layer on a surface of the die, and extending at least between opposite lateral sides of the die, a second material layer comprising a second metal over the first material layer, and a third material layer comprising silver particles and having a porosity greater than that of the second material layer, the third material layer between the first material layer and the second material layer. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 8, 2019Publication date: September 10, 2020Applicant: Intel CorporationInventors: Elizabeth Nofen, James C. Matayabas, JR., Yawei Liang, Yiqun Bai
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Publication number: 20200273768Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Publication number: 20200273772Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 27, 2019Publication date: August 27, 2020Applicant: Intel CorporationInventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
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Publication number: 20200227332Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.Type: ApplicationFiled: January 10, 2019Publication date: July 16, 2020Applicant: Intel CorporationInventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR.
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Patent number: 10115606Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include modifying an underfill material with one of a thiol adhesion promoter, an azole coupling agent, surface modified filler, and peroxide based cross-linking polymer chemistries to greatly enhance adhesion in package structures utilizing the embodiments herein.Type: GrantFiled: April 26, 2016Date of Patent: October 30, 2018Assignee: Intel CorporationInventors: Yiqun Bai, Yuying Wei, Arjun Krishnan, Suriyakala Ramalingam, Yonghao Xiu, Beverly J. Canham, Sivakumar Nagarajan, Saikumar Jayaraman, Nisha Ananthakrishnan
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Patent number: 9704767Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).Type: GrantFiled: December 23, 2015Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Suriyakala Ramalingam, Yiqun Bai, Nisha Ananthakrishnan, Arjun Krishnan
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Publication number: 20170186658Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Suriyakala RAMALINGAM, Yiqun BAI, Nisha ANANTHAKRISHNAN, Arjun KRISHNAN
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Patent number: 9611372Abstract: An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight % of the underfill composition. The filler particles comprise first filler particles having a particle size of from 0.1 micrometers to 15 micrometers and second filler particles having a particle size of less than 100 nanometers. A viscosity of the underfill composition is less than a viscosity of a corresponding composition not including the second filler particles.Type: GrantFiled: February 19, 2016Date of Patent: April 4, 2017Assignee: Intel CorporationInventors: Yonghao Xiu, Nisha Ananthakrishnan, Yiqun Bai, Arjun Krishnan