Abstract: A satellite corrections generation system receives reference receiver measurement information from a plurality of reference receivers at established locations. In accordance with the received reference receiver measurement information, and established locations of the reference receivers, the system determines narrow-lane navigation solutions for the plurality of reference receivers. The system also determines, in accordance with the narrow-lane navigation solutions, at a first update rate, an orbit correction for each satellite of a plurality of satellites; at a second update rate, a clock correction for each such satellite; and at a third update rate that is faster than the second update rate, an update to the clock correction for each such satellite. Further, the system generates navigation satellite corrections for each such satellite, including the orbit correction updated at the first update rate, and the clock correction that is updated at the third update rate.

Abstract: A moveable object determines a preliminary position for the moveable object using received satellite navigation signals and satellite orbit correction information and satellite clock correction information. A position correction is determined by identifying which cell, of a predefined set of geographical cells, corresponds to the determined preliminary position, and obtaining from a database, pre-computed tectonic terrestrial plate position information for the identified cell. Based on the information for the identified cell, a tectonic terrestrial plate, corresponding to the determined preliminary position of the moveable object is identified.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor substrate that includes a first substrate region, a second substrate region, and a third substrate region; providing a first mask that overlaps the semiconductor substrate; etching, using the first mask, the first semiconductor substrate to form a trench in each of the substrate regions; providing a second mask that overlaps the semiconductor substrate and includes three openings corresponding to the substrate regions; performing first ion implantation through the three openings to form a P-doped region in each of the substrate regions; performing second ion implantation through the three openings to form an N-doped region in each of the substrate regions; and performing third ion implantation through the three openings to form another N-doped region in each of the substrate regions; and forming an isolation member in each of the trenches.

Abstract: A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor substrate that includes a first substrate region, a second substrate region, and a third substrate region; providing a first mask that overlaps the semiconductor substrate; etching, using the first mask, the first semiconductor substrate to form a trench in each of the substrate regions; providing a second mask that overlaps the semiconductor substrate and includes three openings corresponding to the substrate regions; performing first ion implantation through the three openings to form a P-doped region in each of the substrate regions; performing second ion implantation through the three openings to form an N-doped region in each of the substrate regions; and performing third ion implantation through the three openings to form another N-doped region in each of the substrate regions; and forming an isolation member in each of the trenches.

Abstract: A method is provided for fabricating a metal interconnection structure. The method includes providing a semiconductor substrate having an active region and an isolation structure surrounding the active region; and forming a metal layer on a surface of the semiconductor substrate. The method also includes forming a metal silicide layer on the active region by a reaction of the metal layer and material of the active regions; and forming an inter metal connection layer electrically connecting with the active regions on the isolation structure. Further, the method includes forming a dielectric layer covering the metal silicide layer, the isolation structure and the inter metal connection layer on the semiconductor substrate; and forming a metal contact via electrically connecting with the active region through the inter metal connection layer in the dielectric layer.

Abstract: Semiconductor devices and fabrication methods are disclosed. A mask layer having an opening is formed on a semiconductor substrate. The semiconductor substrate is etched along the opening of the mask layer to form a trench therein. The mask layer is laterally etched from the opening of the mask layer along a top surface of the semiconductor substrate to expose a surface portion of the semiconductor substrate on each side of the opening. A liner oxide layer is formed by a thermal oxidation process on interior surface of the trench and on the exposed surface portion of the semiconductor substrate. The thermal oxidation process is controlled such that an upper corner between the top surface of the semiconductor substrate and the trench is rounded after the liner oxide layer is formed. An insulation layer is formed on the liner oxide layer and fills the trench.

Abstract: A satellite clock error is determined for each navigation satellite based on the pseudo-range code measurements, the carrier phase measurements, and broadcast satellite clock errors provided by a receiver network. Differences are determined between the computed satellite clock errors and the broadcast clock errors for each satellite. For each constellation, a clock reference satellite is selected from among the navigation satellites, where the clock reference satellite has the median value of clock error difference for that satellite constellation. A correction is determined for the broadcast clock error by applying a function of the reference satellite's clock error to the broadcast clock error for each satellite in the one or more constellations.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: A satellite clock error is determined for each navigation satellite based on the pseudo-range code measurements, the carrier phase measurements, and broadcast satellite clock errors provided by a receiver network. Differences are determined between the computed satellite clock errors and the broadcast clock errors for each satellite. For each constellation, a clock reference satellite is selected from among the navigation satellites, where the clock reference satellite has the median value of clock error difference for that satellite constellation. A correction is determined for the broadcast clock error by applying a function of the reference satellite's clock error to the broadcast clock error for each satellite in the one or more constellations.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: The present invention discloses a method of fabricating mirrors for LCOS (Liquid Crystal On Silicon) display device, including: forming a dielectric layer over a silicon substrate; forming a stop layer over the dielectric layer; forming an insulation layer over the stop layer; etching the insulation layer and the stop layer until the dielectric layer is exposed, thus forming an insulation fence; forming a metal layer over the dielectric layer and the insulation fence; and planarizing the metal layer and the insulation fence, hence the planarized insulation fence isolating the metal layer into mirror array. Therefore no pits can be generated in the metal layer and no pits can be generated in the mirrors formed subsequently, resulting in high quality mirror surface.

Abstract: The present invention discloses a method of fabricating mirrors for LCOS (Liquid Crystal On Silicon) display device, including: forming a dielectric layer over a silicon substrate; forming a stop layer over the dielectric layer; forming an insulation layer over the stop layer; etching the insulation layer and the stop layer until the dielectric layer is exposed, thus forming an insulation fence; forming a metal layer over the dielectric layer and the insulation fence; and planarizing the metal layer and the insulation fence, hence the planarized insulation fence isolating the metal layer into mirror array. Therefore no pits can be generated in the metal layer and no pits can be generated in the mirrors formed subsequently, resulting in high quality mirror surface.

Abstract: An embodiment of the present invention discloses a Liquid Crystal on Silicon (LCOS) display unit, in which a Metal-Insulator-Metal (MIM) capacitor consisting of a micromirror layer, a insulation layer and a light shielding layer is formed by grounding the light shielding layer on a pixel switch circuit layer. Therefore the pixel switch circuit and the capacitor are in vertical distribution, that is, the switch circuit and the capacitor both have an allowable design area of the size of one pixel. Another embodiment of the present invention provides a method for forming a Liquid Crystal on Silicon (LCOS) display unit.

Abstract: The invention discloses a planarization method for a wafer having a surface layer with a recess, comprises: forming an etching-resist layer on the surface layer to fill the entire recess; etching the etching-resist layer and the surface layer, till the surface layer outside the recess is flush to or lower than the bottom of the recess, the etching speed of the surface layer being higher than that of the etching-resist layer; removing the etching-resist layer; and etching the surface layer to a predetermined depth. The method can avoid concentric ring recesses on the surface of the wafer resulted from a chemical mechanical polishing (CMP) process in the prior art, and can be used to obtain a wafer surface suitable for optical applications.