Abstract: A power supply apparatus, including: a transformer including a first primary winding for connection to a first power source and a second primary winding for connection to a second power source, and a secondary winding for delivering power therefrom as the output of the power supply apparatus; a controller for receiving voltage inputs from the first power source and the second power source, and in response to the received voltage inputs control supply from the first power source to the first primary winding and from the second power source to the second primary winding, such that: if the first power source and second power source are available the controller operates to allow power to be supplied to the first primary winding from the first power source and operates to shut off supply of power to the second primary winding from the second power source.

Abstract: A protection circuit including an inrush current detector operable to detect an inrush current from a DC link is disclosed herein. The inrush current detector includes a transistor switch that is turned on in normal operation of the protection circuit. The protection circuit operates to detect when the voltage across the transistor switch exceeds a threshold voltage in response to a detected inrush current, and in response operates to turn off the transistor switch.

Abstract: A power supply conversion topology of a multiphase switch capacitor resonant cavity conversion circuit with full-wave output rectification. The power supply conversion topology includes at least k conversion switch capacitors and one output switch capacitor which are sequentially connected in series through conductors and are connected to two ends of input power supply. When a transformer ratio N is an even number, k=N/2; when transformer ratio N is not an even number, k is smallest integral greater than N/2; and lower end of output switch capacitor is grounded, and two ends of output switch capacitor are connected with output interfaces. Power supply conversion topology further includes k switch resonant cavity converters. When transformer ratio N is even number, k=N/2; and when transformer ratio N is not even number, k is smallest integral greater than N/2. The invention further discloses two power supply conversion structures based on power supply conversion topology.

Abstract: A protection circuit including an inrush current detector operable to detect an inrush current from a DC link is disclosed herein. The inrush current detector includes a transistor switch that is turned on in normal operation of the protection circuit. The protection circuit operates to detect when the voltage across the transistor switch exceeds a threshold voltage in response to a detected inrush current, and in response operates to turn off the transistor switch.

Abstract: A power supply apparatus, including: a transformer including a first primary winding for connection to a first power source and a second primary winding for connection to a second power source, and a secondary winding for delivering power therefrom as the output of the power supply apparatus; a controller for receiving voltage inputs from the first power source and the second power source, and in response to the received voltage inputs control supply from the first power source to the first primary winding and from the second power source to the second primary winding, such that: if the first power source and second power source are available the controller operates to allow power to be supplied to the first primary winding from the first power source and operates to shut off supply of power to the second primary winding from the second power source.

Abstract: A two-dimensional accessible non-volatile memory apparatus includes an array comprising a plurality of non-volatile memory cells, the array being a crossbar-based non-volatile memory structure, the memory cells being arranged in a plurality of rows and a plurality of columns. The apparatus further includes row read/write circuitry coupled to the array and structured and configured to provide read and write access to the memory cells in any one of the rows on an individual row basis, and column read/write circuitry coupled to the array and structured and configured to provide read and write access to the memory cells in any one of the columns on an individual column basis.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

Abstract: A two-dimensional accessible non-volatile memory apparatus includes an array comprising a plurality of non-volatile memory cells, the array being a crossbar-based non-volatile memory structure, the memory cells being arranged in a plurality of rows and a plurality of columns. The apparatus further includes row read/write circuitry coupled to the array and structured and configured to provide read and write access to the memory cells in any one of the rows on an individual row basis, and column read/write circuitry coupled to the array and structured and configured to provide read and write access to the memory cells in any one of the columns on an individual column basis.

Abstract: A memory device, such as an FeDRAM device, includes a memory array including a plurality of rows, each row having a plurality of storage elements (e.g., FeFETs). The memory device further includes a plurality of refresh trigger circuits, each refresh trigger circuit being associated with a respective one of the rows. Each refresh trigger circuit is structured to produce an output signal indicative of an estimated degradation of a memory window of one or more of the storage elements of the associated one of the rows. The memory device also further includes control circuitry coupled to each of the refresh trigger circuits, wherein the control circuitry is structured and configured to determine whether to initiate a refresh of the storage elements of a particular one of the rows based on the output signal produced by the refresh trigger circuit associated with the particular one of the rows.

Abstract: A memory device, such as an FeDRAM device, includes a memory array including a plurality of rows, each row having a plurality of storage elements (e.g., FeFETs). The memory device further includes a plurality of refresh trigger circuits, each refresh trigger circuit being associated with a respective one of the rows. Each refresh trigger circuit is structured to produce an output signal indicative of an estimated degradation of a memory window of one or more of the storage elements of the associated one of the rows. The memory device also further includes control circuitry coupled to each of the refresh trigger circuits, wherein the control circuitry is structured and configured to determine whether to initiate a refresh of the storage elements of a particular one of the rows based on the output signal produced by the refresh trigger circuit associated with the particular one of the rows.

Abstract: Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.

Abstract: A method of reading a memory cell of a magneto-resistive random access memory device, wherein the memory cell has a ferromagnetic free layer having a first magnetization orientation and a ferromagnetic reference layer, includes applying a first read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a first voltage generated by the memory cell in response to the first read current, generating a magnetic field adjacent to the memory cell, the magnetic field having a second magnetization orientation that is not parallel to the first magnetization orientation, while the magnetic field is being generated, applying a second read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a second voltage generated by the memory cell in response to the second read current, and determining a state of the memory cell based on the first voltage and the second voltage.

Abstract: Invention provides an apparatus and method for performing signal processing on a crossbar array of resistive memory devices. The invention is implemented using one or multiple crossbar arrays of resistive memory devices in conjunction with devices for converting input real number representations to voltage waveforms, devices for converting current waveforms into voltage waveforms, and devices for converting voltage waveforms to real numbers outputs.

Abstract: A method of reading a memory cell of a magneto-resistive random access memory device, wherein the memory cell has a ferromagnetic free layer having a first magnetization orientation and a ferromagnetic reference layer, includes applying a first read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a first voltage generated by the memory cell in response to the first read current, generating a magnetic field adjacent to the memory cell, the magnetic field having a second magnetization orientation that is not parallel to the first magnetization orientation, while the magnetic field is being generated, applying a second read current from the ferromagnetic free layer to the ferromagnetic reference layer and storing a second voltage generated by the memory cell in response to the second read current, and determining a state of the memory cell based on the first voltage and the second voltage.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

Abstract: Embodiments of techniques or systems for usage modeling or gesture based authentication are provided herein. Actions of a user may be captured, classified, and utilized to generate an authentication scheme for a device based on gesture recognition, gesture analysis, or action analysis. Training data may be determined based on actions deemed to be training actions and one or more action models may be generated based on the training data. An action model may be indicative of how a user performs a particular or predetermined action. When a security mode is enabled, usage actions may be recorded and usage data may be extracted or determined based on the usage actions. A usage action may be identified and corresponding usage data may be compared with training data from an appropriate action model. An identity of a user associated with the usage action may be determined based on this comparison.

Abstract: An apparatus that performs the mathematical matrix-vector multiplication approximation operations using crossbar arrays of resistive memory devices (e.g. memristor, resistive random-access memory, spintronics, etc.). A crossbar array formed by resistive memory devices serves as a memory array that stores the coefficients of a matrix. Combined with input and output analog circuits, the crossbar array system realizes the method of performing matrix-vector multiplication approximation operations with significant performance, area and energy advantages over existing methods and designs. This invention also includes an extended method that realizes the auto-associative neural network recall function using the resistive memory crossbar architecture.

Abstract: Various embodiments of the present invention are generally directed to an apparatus and associated method for updating data in a non-volatile memory array. In accordance with some embodiments, a memory block is formed with a plurality of types of memory cell sectors arranged in data pages of a first type and log pages of a second type that can be updated in-place. A first updated sector is written to a first log page while maintaining an outdated sector in an original data page, and overwritten with a second updated sector.

Abstract: Devices and methods for generating a random number that utilizes a magnetic tunnel junction are disclosed. An AC current source can be in electrical connection to a magnetic tunnel junction to provide an AC current to the magnetic tunnel junction. A read circuit can be used to determine a bit based on a state of the magnetic tunnel junction. A rate of production of the bits can be adjusted, such as by adjusting a frequency or amplitude of the AC current. A probability of obtaining a “0” or “1” bit can be managed, such as by an addition of DC biasing to the AC current.

Abstract: Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems. Invention provides iterative training of memristor crossbar arrays for neural networks by applying voltages corresponding to selected training patterns. Error is detected and measured as a function of the actual response to the training patterns versus the expected response to the training pattern.