Abstract: Self-reference reading a magnetic tunnel junction data cell methods are disclosed. An illustrative method includes applying a read voltage across a magnetic tunnel junction data cell and forming a read current. The magnetic tunnel junction data cell has a first resistance state. The read voltage is sufficient to switch the magnetic tunnel junction data cell resistance. The method includes detecting the read current and determining if the read current remains constant during the applying step. If the read current remains constant during the applying step, then the first resistance state of the magnetic tunnel junction data cell is the resistance state that the read voltage was sufficient to switch the magnetic tunnel junction data cell to.

Abstract: A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state. The first read current is less than the second read current. Then the first bit line read voltage is compared with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.

Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

Abstract: A method and apparatus for using thermal preconditioning to write data to a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM) memory cell. In some embodiments, a logical state is written to an unconditioned non-volatile first memory cell associated with a first block address. Thermal preconditioning is concurrently applied to a non-volatile second memory cell associated with a second block address selected in response to the first block address.

Abstract: The present disclosure relates to methods of selectively placing a reference column or reference row in a memory array. The method includes measuring a resistance state resistance value for a plurality of variable resistive memory cells within a memory array and mapping a location of each measured variable resistive memory cell to form a map of the resistance state resistance values for a plurality of variable resistive memory cells within a memory array. Then a column or row is selected to be a reference column or reference row based on the map of the resistance state resistance value for a plurality of variable resistive memory cells within a memory array, to minimize read operation errors, and forming a variable resistive memory cell memory array.

Abstract: A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.

Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.

Abstract: Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

Abstract: An apparatus and method for compensating for asymmetric write current in a non-volatile unit cell. The unit cell comprises a switching device and an asymmetric resistive sense element (RSE), such as an asymmetric resistive random access memory (RRAM) element or an asymmetric spin-torque transfer random access memory (STRAM) element. The RSE is physically oriented within the unit cell relative to the switching device such that a hard direction for programming the RSE is aligned with an easy direction of programming the unit cell, and an easy direction for programming the RSE is aligned with a hard direction for programming the unit cell.

Abstract: A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.

Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.

Abstract: The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

Abstract: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.

Abstract: Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.

Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.

Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.

Abstract: Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

Abstract: A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.

Abstract: A magnetic memory device includes a magnetic tunnel junction having a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation and a memristor solid state element electrically coupled to the magnetic tunnel junction. The memristor has a device response that is an integrated voltage versus an integrated current.