Patents by Inventor Yisuo Li
Yisuo Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110303973Abstract: The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.Type: ApplicationFiled: May 26, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, King-Jien Chui, Yisuo Li, Yu Jiang, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Publication number: 20110303985Abstract: The semiconductor device includes: a columnar silicon layer on the planar silicon layer; a first n+ type silicon layer formed in a bottom area of the columnar silicon layer; a second n+ type silicon layer formed in an upper region of the columnar silicon layer; a gate insulating film formed in a perimeter of a channel region between the first and second n+ type silicon layers; a gate electrode formed in a perimeter of the gate insulating film, and having a first metal-silicon compound layer; an insulating film formed between the gate electrode and the planar silicon layer, an insulating film sidewall formed in an upper sidewall of the columnar silicon layer; a second metal-silicon compound layer formed in the planar silicon layer; and an electric contact formed on the second n+ type silicon layer.Type: ApplicationFiled: May 23, 2011Publication date: December 15, 2011Inventors: Fujio Masuoka, Hiroki Nakamura, Shintaro Arai, Tomohiko Kudo, Yu Jiang, King-Jien Chui, Yisuo Li, Xiang Li, Zhixian Chen, Nansheng Shen, Vladimir Bliznetsov, Kavitha Devi Buddharaju, Navab Singh
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Patent number: 7951680Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.Type: GrantFiled: October 30, 2008Date of Patent: May 31, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Guowei Zhang, Yisuo Li, Ming Li, Purakh Raj Verma, Shao-fu Sanford Chu
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Publication number: 20110079850Abstract: A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.Type: ApplicationFiled: December 10, 2010Publication date: April 7, 2011Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Jeoung Mo KOO, Purakh Raj VERMA, Sanford CHU, Chunlin ZHU, Yisuo LI
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Publication number: 20110042743Abstract: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprise forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate.Type: ApplicationFiled: November 1, 2010Publication date: February 24, 2011Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Sanford CHU, Yisuo LI, Guowei ZHANG, Purakh Raj VERMA
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Patent number: 7888752Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.Type: GrantFiled: February 14, 2007Date of Patent: February 15, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee
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Patent number: 7867862Abstract: A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.Type: GrantFiled: September 14, 2007Date of Patent: January 11, 2011Assignee: Chartered Semiconductor Manufacturing, LtdInventors: Jeoung Mo Koo, Purakh Raj Verma, Sanford Chu, Chunlin Zhu, Yisuo Li
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Patent number: 7824968Abstract: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate. The stress layer and the dummy gate improve the stress in the channel and offset drain region.Type: GrantFiled: July 17, 2006Date of Patent: November 2, 2010Assignee: Chartered Semiconductor Manufacturing LtdInventors: Sanford Chu, Yisuo Li, Guowei Zhang, Purakh Raj Verma
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Publication number: 20100109045Abstract: An integrated circuit system that includes: providing a substrate including an active device; forming a trench within the substrate adjacent the active device; forming a first layer with a first lattice constant within the trench; and forming a second layer with a second lattice constant over the first layer, the second lattice constant differing from the first lattice constant.Type: ApplicationFiled: October 30, 2008Publication date: May 6, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Jin Ping Liu, Yisuo Li, Alex K.H. See, Meisheng Zhou, Liang-Choo Hsia
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Publication number: 20100109097Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.Type: ApplicationFiled: October 30, 2008Publication date: May 6, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Guowei Zhang, Yisuo Li, Ming Li, Purakh Raj Verma, Shao-fu Sanford Chu
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Publication number: 20090302385Abstract: An LDMOS device includes a substrate having a surface and a gate electrode overlying the surface and defining a channel region in the substrate below the gate electrode. A drain region is spaced apart from the channel region by an isolation region. The isolation region includes a region of high tensile stress and is configured to induce localized stress in the substrate in close proximity to the drain region. The region of high tensile stress in the isolation region can be formed by high-stress silicon oxide or high-stress silicon nitride. In a preferred embodiment, the isolation region is a shallow trench isolation region formed in the substrate intermediate to the gate electrode and the drain region.Type: ApplicationFiled: June 6, 2008Publication date: December 10, 2009Inventors: Sanford Chu, Yisuo Li, Guowei Zhang, Verma Purakh
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Patent number: 7573099Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.Type: GrantFiled: June 28, 2005Date of Patent: August 11, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Yisuo Li, Xiaohong Jiang, Francis Benistant
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Publication number: 20090072310Abstract: A high voltage device includes a substrate with a device region defined thereon. A gate stack is disposed on the substrate in the device region. A channel region is located in the substrate beneath the gate stack, while a first diffusion region is located in the substrate on a first side of the gate stack. A first isolation structure in the substrate, located on the first side of the gate stack, separates the channel and the first diffusion region. The high voltage device also includes a first drift region in the substrate coupling the channel to the first diffusion region, wherein the first drift region comprises a non-uniform depth profile conforming to a profile of the first isolation structure.Type: ApplicationFiled: September 14, 2007Publication date: March 19, 2009Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Jeoung Mo KOO, Purakh Raj VERMA, Sanford CHU, Chunlin ZHU, Yisuo LI
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Publication number: 20080014690Abstract: First example embodiments comprise forming a stress layer over a MOS transistor (such as a LDMOS Tx) comprised of a channel and first, second and third junction regions. The stress layer creates a stress in the channel and the second junction region of the Tx. Second example embodiments comprises forming a MOS FET and at least a dummy gate over a substrate. The MOS is comprised of a gate, channel, source, drain and offset drain. At least one dummy gate is over the offset drain. A stress layer is formed over the MOS and the dummy gate.Type: ApplicationFiled: July 17, 2006Publication date: January 17, 2008Inventors: Sanford Chu, Yisuo Li, Guowei Zhang, Purakh Raj Verma
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Publication number: 20070210376Abstract: An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.Type: ApplicationFiled: March 8, 2007Publication date: September 13, 2007Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Yisuo Li, Gang Chen, Francis Benistant, Purakh Raj Verma, Hong Yang, Shao-fu Sanford Chu
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Patent number: 7259072Abstract: A method is described to fabricate a MOSFET device with increased threshold voltage stability. After the pad oxide and pad nitride are deposited on the silicon substrate and shallow trenches are patterned and the pad nitride removed. As+ or P+ species are then implanted using low energy ions of approximately 5 keV into the pad oxide. Conventional As+ or P+ implant follows the shallow implant to form the n-wells. With this procedure of forming a sacrificial shallow implantation oxide layer, surface dopant concentration variation at pad oxide:silicon substrate interface is minimized; and threshold voltage stability variation of the device is significantly decreased.Type: GrantFiled: April 21, 2004Date of Patent: August 21, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yisuo Li, Francis Benistant, Kim Hyun Sik, Zhao Lun
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Patent number: 7253483Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.Type: GrantFiled: June 27, 2005Date of Patent: August 7, 2007Assignee: Chartered Semiconductor Manufacturing, LTDInventors: Yisuo Li, Xiaohong Jiang, Francis Benistant
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Publication number: 20070178652Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.Type: ApplicationFiled: February 14, 2007Publication date: August 2, 2007Inventors: King Chui, Francis Benistant, Ganesh Samudra, Kian Tee, Yisuo Li, Kum Woh Leong, Kheng Tee
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Patent number: 7202133Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.Type: GrantFiled: January 21, 2004Date of Patent: April 10, 2007Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee
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Patent number: 7101743Abstract: A method for forming elevated source/drain regions. A gate structure is formed over a substrate. The substrate comprised of silicon. We form a polysilicon layer preferably using PVD or CVD over the gate structure and the substrate. A poly/Si interface is formed between the polysilicon layer and the substrate. We perform a poly/Si interface amorphization implant to amorphize at least the poly/Si interface in the S/D areas and to from an amorphous region. We anneal the substrate to crystallize the amorphous region and the polysilicon layer over the amorphous region to form an elevated silicon region in the source/drain area. Next, source/drain regions in are formed in the elevated silicon regions and the substrate.Type: GrantFiled: January 6, 2004Date of Patent: September 5, 2006Assignee: Chartered Semiconductor Manufacturing L.T.D.Inventors: Yisuo Li, Francis Benistant, Kian Meng Tee, King Jien Chui