Abstract: A semiconductor memory device includes a plurality of word lines each of which are connected to a plurality of memory cells, a row control unit suitable for sequentially activating and precharging a word line corresponding to a target address and a predetermined (N) number of adjacent word lines during a target activation mode, and a mode exit control unit suitable for counting the number of activation operations by the row control unit during the target activation mode to determine whether or not to exit from the target activation mode.

Abstract: A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.

Abstract: A memory device includes a plurality of memory blocks configured to be refreshed in response to respective refresh signals; a command decoder configured to decode an external input command to generate an internal refresh command; a refresh control unit configured to activate a first number of refresh signals corresponding to the first number of memory blocks when the internal refresh command is activated and a first mode is set, and to activate a second number of refresh signals corresponding to the second number of memory blocks when the internal refresh command is activated and a second mode is set, the second number being smaller than the first number; and an address counter configured to change the row address transferred to the memory blocks when a predetermined one of the refresh signals is activated.

Abstract: A memory device includes a plurality of memory blocks, a setting circuit configured to set a first mode, in which a first number of memory blocks are refreshed at a time, and a second mode, in which a second number of memory blocks are refreshed at a time, under control of a memory controller, the second number being smaller than the first number, a storage circuit configured to store additional refresh information, and a refresh control unit configured to control the second number of memory blocks to be refreshed at a time whenever a refresh command is applied when the additional refresh information is deactivated, and to control the first number of memory blocks to be refreshed at a time whenever the refresh command is applied when the additional refresh information is activated in a case in which the second mode is set by the setting circuit.

Abstract: A refresh control circuit includes an internal chip information unit configured to provide internal chip information related to a retention characteristic of a memory cell, a mode information modification unit configured to output modified mode information based on the internal chip information, wherein the modified mode information represent a number of memory banks for refresh operation, and a selection signal activation unit configured to activate one or more of selection signals for selecting corresponding one or more of the memory banks in response to the modified mode information.