Abstract: A power divider includes an input capacitor, and first and second transmission lines (TLs). The first TL includes an input portion (IP), a transmission portion (TP) and an output portion (OP). The second TL includes a TP and an OP. The IP is for receiving an input signal, and is connected to the TPs of the first and second TLs. For each of the first and second TLs, the TP has a length that is one-twelfth of a target wavelength, and is connected to the OP. The OPs of the first and second TLs are for cooperatively outputting a pair of output signals which are in-phase and each of which has a frequency equal to that of the input signal. The input capacitor is connected between ground and the IP.

Abstract: A power divider includes first to third transmission lines (TLs) and first to third capacitors. The second TL includes a first transmission portion (TP) and a first output portion (OP). The first TP is connected between the first TL and the first OP. The third TL includes a second TP and a second OP. The second TP is connected between the first TL and the second OP. The first capacitor is connected between ground and a common node of the first TL and the first and second TPs. The second capacitor is connected between ground and a terminal of the first OP distal from the first TP. The third capacitor is connected between ground and a terminal of the second OP distal from the second TP.

Abstract: A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

Abstract: A power divider/combiner includes a first transmission line that includes a first part and a second part, and a second transmission line and a third transmission line that are electromagnetically coupled with the first transmission line. The first part, the second part, the second transmission line and the third transmission line are each of a particular length. The first part, the second transmission line and the third transmission line are respectively connected to a first port, a second port and a third port for inputting/outputting signals having a target wavelength equal to four times the particular length.

Abstract: A transistor comprises a drain, a gate, a source, a body terminal and a body resistance. The drain is connected to a supply voltage line to receive a supply voltage. The gate is connected to a control voltage line to receive a control voltage. The source is connected to a input line to receive a input radio frequency signal. The body terminal is connected to the drain. The body resistance is disposed between the drain and the body terminal. By the foregoing configuration, the leakage current of the substrate is reduced and the threshold voltage of the transistor is reduced to conform to the present low power design.

Abstract: A power divider includes an input capacitor, and first and second transmission lines (TLs). The first TL includes an input portion (IP), a transmission portion (TP) and an output portion (OP). The second TL includes a TP and an OP. The IP is for receiving an input signal, and is connected to the TPs of the first and second TLs. For each of the first and second TLs, the TP has a length that is one-twelfth of a target wavelength, and is connected to the OP. The OPs of the first and second TLs are for cooperatively outputting a pair of output signals which are in-phase and each of which has a frequency equal to that of the input signal. The input capacitor is connected between ground and the IP.

Abstract: A down-conversion mixer includes a converting-and-mixing circuit and a load circuit. The converting-and-mixing circuit performs voltage to current conversion and mixing with a differential oscillatory voltage signal pair upon a differential input voltage signal pair to generate a differential mixed current signal pair. The load circuit includes two transistors each having a transconductance that varies according to a control voltage, two resistors each decreasing a threshold voltage of a respective one of the transistors, and a resistor-inductor circuit cooperating with the transistors to convert the differential mixed current signal pair into a differential mixed voltage signal pair.

Abstract: A power divider/combiner includes a first transmission line that includes a first part and a second part, and a second transmission line and a third transmission line that are electromagnetically coupled with the first transmission line. The first part, the second part, the second transmission line and the third transmission line are each of a particular length. The first part, the second transmission line and the third transmission line are respectively connected to a first port, a second port and a third port for inputting/outputting signals having a target wavelength equal to four times the particular length.

Abstract: A power divider includes two transmission lines (TLs), two capacitors and a resistor. Each TL has a first terminal, a second terminal, and a length that is 0.07 to 0.12 times an operation wavelength in the power divider. The TLs establish electromagnetic coupling therebetween. The first terminals of the TLs are connected together, and are to receive an input signal. One of the capacitors is connected to a common node of the TLs. The other capacitor and the resistor are connected in parallel between the second terminals of the TLs. The second terminals of the TLs are to respectively provide two output signals which are in-phase, and each of which has a frequency equal to that of the input signal.

Abstract: A power divider/combiner includes a first transmission line (TL) and two second TLs. The first TL has a first terminal that is for receiving or outputting a signal with a target wavelength, and a second terminal that is open circuited. Each of the second TLs is disposed adjacent to and spaced apart from the first TL so as to establish electromagnetic coupling therebetween. Each of the second TLs has a first terminal, and a second terminal that is distal from the first terminal of the first TL. The second terminals of the second Its are for cooperatively outputting or receiving a pair of signals that have the target wavelength and that are in-phase. Each of the first and second TLs has a length that is a quarter of the target wavelength.

Abstract: A power divider/combiner includes a first transmission line (TL) and two second TLs. The first TL has a first terminal that is for receiving or outputting a signal with a target wavelength, and a second terminal that is open circuited. Each of the second TLs is disposed adjacent to and spaced apart from the first TL so as to establish electromagnetic coupling therebetween. Each of the second TLs has a first terminal, and a second terminal that is distal from the first terminal of the first TL. The second terminals of the second TLs are for cooperatively outputting or receiving a pair of signals that have the target wavelength and that are in-phase. Each of the first and second TLs has a length that is a quarter of the target wavelength.

Abstract: An injection locked frequency divider includes: a resonator circuit including first to fourth inductors; and a mixer circuit receiving an input signal with an input frequency. Each of the third and fourth inductors is coupled between a respective one of the first and second inductors and the mixer circuit. The two circuits cooperate to form a tank circuit having a free-running frequency and defining a frequency locking range which is around three times the free-running frequency and within which the input frequency falls. By at least performing mixing with a differential reference signal pair, the mixer circuit generates, based on the input signal, a differential mixed signal pair with a frequency that is one-third the input frequency.

Abstract: A down-conversion mixer includes a converting-and-mixing module and a load module. The converting-and-mixing module performs voltage-to-current conversion and mixing with first and second differential oscillatory voltage signal pairs upon a differential input voltage signal pair to generate first and second differential mixed current signal pairs. The load module includes two RL circuits and a negative resistance providing circuit that cooperate to convert the first and second differential mixed current signal pairs into first and second differential mixed voltage signal pairs. Each RL circuit includes two variable resistors, and an inductor connected between the variable resistors.

Abstract: A radio-frequency/direct-current (RF/DC) converter is operable to receive a high-frequency and high-power RF signal and convert to a DC power. The RF/DC converter includes a first field-effect transistor (FET), a second FET, a third FET and a sixth FET that are cross-coupled. Sources of the first FET and the second FET are connected to an RF signal receiving end. Sources of the third FET and the fourth FET are connected to a potential reference end. The RF/DC converter further includes a fifth FET and a sixth FET connected subsequently to the first FET, the second FET, the third FET and the fourth.

Abstract: A down-conversion mixer includes a converting-and-mixing module and a load module. The converting-and-mixing module performs voltage-to-current conversion and mixing with a differential oscillatory voltage signal pair upon a differential input voltage signal pair to generate a differential mixed current signal pair. The load module includes a first transistor, a second transistor and a resistor-inductor (RL) circuit that cooperatively convert the differential mixed current signal pair into a differential mixed voltage signal pair. Each of the first and second transistors has a transconductance that varies according to a control voltage.

Abstract: An N-way RF power amplifier device includes a power divider, multiple first power amplifier circuits, multiple second power amplifier circuits, and a power combiner. The power divider divides an RF input signal into multiple differential signal pairs each including complementary first and second division signals. The first power amplifier circuits amplify the first division signals and the second power amplifier circuits amplify the second division signals in such a way that the amplified first division signals and the amplified second division signals have the same phase. The power combiner combines the amplified first and second division signals into an RF output signal.

Abstract: A radio-frequency (RF) transceiver front-end circuit includes an antenna, a power amplifier, a low-noise amplifier, a first switch unit and a second switch unit. The power amplifier is connected to a transmitting unit and the antenna to form a transmission path. The low-noise amplifier is connected to a receiving unit and the antenna to form a reception path. The transmission path and the reception path selectively do not include a ?/4 transmission line connected to the antenna. The RF transceiver front-end circuit has a receiving state and a transmitting state. In the receiving state, the first switch unit is controlled and causes the transmission path to have high impedance. In the transmitting state, the second switch unit is controlled and causes the reception path to have high impedance.

Abstract: An N-way RF power amplifier device includes a power divider, multiple first power amplifier circuits, multiple second power amplifier circuits, and a power combiner. The power divider divides an RF input signal into multiple differential signal pairs each including complementary first and second division signals. The first power amplifier circuits amplify the first division signals and the second power amplifier circuits amplify the second division signals in such a way that the amplified first division signals and the amplified second division signals have the same phase. The power combiner combines the amplified first and second division signals into an RF output signal.

Abstract: A frequency divider includes a signal injection circuit and an oscillating circuit. The signal injection circuit includes a transistor of which a gate receives an input signal with an input frequency, a drain and a source cooperatively provide a first differential signal pair, and a body receives a biasing voltage. The two circuits cooperate to form a tank circuit having a free-running frequency and defining a frequency locking range which is around N times the free-running frequency and within which the input frequency falls. The tank circuit generates a second differential signal pair that is related to the first differential signal pair and that has an oscillating frequency which is one-Nth the input frequency.

Abstract: A frequency divider includes a signal injection circuit and an oscillating circuit. The signal injection circuit includes a transistor of which a gate receives an input signal with an input frequency, a drain and a source cooperatively provide a first differential signal pair, and a body receives a biasing voltage. The two circuits cooperate to form a tank circuit having a free-running frequency and defining a frequency locking range which is around N times the free-running frequency and within which the input frequency falls. The tank circuit generates a second differential signal pair that is related to the first differential signal pair and that has an oscillating frequency which is one-Nth the input frequency.